reordering_target.h

/*
 * Copyright 2020-2022 Arteris IP
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.axi_util.cpp
 */
#pragma once
 
#include "target_info_if.h"
#include <axi/pe/axi_target_pe.h>

namespace axi {
namespace pe {
class tx_reorderer : public sc_core::sc_module, tlm::scc::pe::intor_fw_nb {
public:
    sc_core::sc_in<bool> clk_i{"clk_i"};
 
    sc_core::sc_export<tlm::scc::pe::intor_fw_nb> fw_i{"fw_i"};
 
    sc_core::sc_port<tlm::scc::pe::intor_bw_nb, 1, sc_core::SC_ZERO_OR_MORE_BOUND> bw_o{"bw_o"};
    sc_core::sc_attribute<unsigned> min_latency{"min_latency", 10};
    sc_core::sc_attribute<unsigned> max_latency{"max_latency", 100};
    sc_core::sc_attribute<unsigned> window_size{"window_size", 2};
    sc_core::sc_attribute<bool> prioritize_by_latency{"prioritize_by_latency", false};
    sc_core::sc_attribute<bool> prioritize_by_qos{"prioritize_by_qos", false};
 
    tx_reorderer(const sc_core::sc_module_name& nm);
    void transport(tlm::tlm_generic_payload& payload, bool lt_transport = false) override;
    void snoop_resp(tlm::tlm_generic_payload& payload, bool sync = false) override {}
 
protected:
    void clock_cb();
    struct que_entry {
        tlm::scc::tlm_gp_shared_ptr trans;
        unsigned age{0};
        que_entry(tlm::tlm_generic_payload& gp)
        : trans(&gp) {}
    };
    std::array<std::unordered_map<unsigned, std::deque<que_entry>>, 3> reorder_buffer;
};

template <unsigned int BUSWIDTH = 32, typename TYPES = axi::axi_protocol_types, int N = 1,
          sc_core::sc_port_policy POL = sc_core::SC_ONE_OR_MORE_BOUND>
class reordering_target : public sc_core::sc_module, public target_info_if {
public:
    using base = axi_target_pe;
    using payload_type = base::payload_type;
    using phase_type = base::phase_type;
 
    sc_core::sc_in<bool> clk_i{"clk_i"};
 
    axi::axi_target_socket<BUSWIDTH, TYPES, N, POL> sckt{"sckt"};

 
    reordering_target(const sc_core::sc_module_name& nm)
    : sc_core::sc_module(nm)
    , pe("pe", BUSWIDTH) {
        sckt(pe);
        pe.clk_i(clk_i);
        pe.fw_o(reorder_buffer.fw_i);
        reorder_buffer.clk_i(clk_i);
        reorder_buffer.bw_o(pe.bw_i);
    }
 
    reordering_target() = delete;
 
    reordering_target(reordering_target const&) = delete;
 
    reordering_target(reordering_target&&) = delete;
 
    reordering_target& operator=(reordering_target const&) = delete;
 
    reordering_target& operator=(reordering_target&&) = delete;
 
    size_t get_outstanding_tx_count() override { return pe.getAllOutStandingTx(); }
 
protected:
    void end_of_elaboration() override {
        auto* ifs = sckt.get_base_port().get_interface(0);
        sc_assert(ifs != nullptr);
        pe.set_bw_interface(ifs);
    }
 
public:
    axi_target_pe pe;
    tx_reorderer reorder_buffer{"reorder_buffer"};
};
} // namespace pe
} // namespace axi