axi_target_pe.h

/*
 * Copyright 2020-2022 Arteris IP
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.axi_util.cpp
 */
 
#pragma once
 
#ifndef SC_INCLUDE_DYNAMIC_PROCESSES
#define SC_INCLUDE_DYNAMIC_PROCESSES
#endif
 
#include <array>
#include <axi/fsm/base.h>
#include <functional>
#include <memory>
#include <scc/mt19937_rng.h>
#include <scc/ordered_semaphore.h>
#include <scc/sc_variable.h>
#include <tlm/scc/pe/intor_if.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include <unordered_set>

namespace axi {
namespace pe {
 
inline unsigned get_cci_randomized_value(cci::cci_param<int> const& p) {
    if(p.get_value() < 0)
        return scc::MT19937::uniform(0, -p.get_value());
    return p.get_value();
}
class axi_target_pe : public sc_core::sc_module, protected axi::fsm::base, public axi::axi_fw_transport_if<axi::axi_protocol_types> {
    struct bw_intor_impl;
 
public:
    using payload_type = axi::axi_protocol_types::tlm_payload_type;
    using phase_type = axi::axi_protocol_types::tlm_phase_type;
 
    sc_core::sc_in<bool> clk_i{"clk_i"};
 
    sc_core::sc_port<tlm::scc::pe::intor_fw_nb, 1, sc_core::SC_ZERO_OR_MORE_BOUND> fw_o{"fw_o"};
 
    sc_core::sc_export<tlm::scc::pe::intor_bw_nb> bw_i{"bw_i"};

    cci::cci_param<unsigned> max_outstanding_tx{"max_outstanding_tx", 0};
    cci::cci_param<bool> rd_data_interleaving{"rd_data_interleaving", true};
    cci::cci_param<int> wr_data_accept_delay{"wr_data_accept_delay", 0};
    cci::cci_param<int> rd_addr_accept_delay{"rd_addr_accept_delay", 0};
    cci::cci_param<int> rd_data_beat_delay{"rd_data_beat_delay", 0};
    cci::cci_param<int> rd_resp_delay{"rd_resp_delay", 0};
    cci::cci_param<int> wr_resp_delay{"wr_resp_delay", 0};
 
    void b_transport(payload_type& trans, sc_core::sc_time& t) override;
 
    tlm::tlm_sync_enum nb_transport_fw(payload_type& trans, phase_type& phase, sc_core::sc_time& t) override;
 
    bool get_direct_mem_ptr(payload_type& trans, tlm::tlm_dmi& dmi_data) override;
 
    unsigned int transport_dbg(payload_type& trans) override;
 
    void set_operation_cb(std::function<unsigned(payload_type& trans)> cb) { operation_cb = cb; }
    void operation_resp(payload_type& trans, unsigned clk_delay = 0);
    bool is_active() { return !active_fsm.empty(); }
    const sc_core::sc_event& tx_finish_event() { return finish_evt; }
 
    ~axi_target_pe();

    explicit axi_target_pe(const sc_core::sc_module_name& nm, size_t transfer_width, flavor_e flavor = flavor_e::AXI);
 
    void set_bw_interface(axi::axi_bw_transport_if<axi_protocol_types>* ifs) { socket_bw = ifs; }
 
    inline unsigned getAllOutStandingTx() const { return outstanding_rd_tx + outstanding_wr_tx + outstanding_ign_tx; }
 
protected:
    axi_target_pe() = delete;
 
    axi_target_pe(axi_target_pe const&) = delete;
 
    axi_target_pe(axi_target_pe&&) = delete;
 
    axi_target_pe& operator=(axi_target_pe const&) = delete;
 
    axi_target_pe& operator=(axi_target_pe&&) = delete;
 
    void end_of_elaboration() override;
 
    void start_of_simulation() override;
 
    void fsm_clk_method() { process_fsm_clk_queue(); }
    fsm::fsm_handle* create_fsm_handle() override;
    void setup_callbacks(fsm::fsm_handle*) override;
 
    unsigned operations_callback(payload_type& trans);
 
    axi::axi_bw_transport_if<axi_protocol_types>* socket_bw{nullptr};
    std::function<unsigned(payload_type& trans)> operation_cb;
    scc::fifo_w_cb<std::tuple<payload_type*, unsigned>> rd_req2resp_fifo{"rd_req2resp_fifo"};
    scc::fifo_w_cb<std::tuple<payload_type*, unsigned>> wr_req2resp_fifo{"wr_req2resp_fifo"};
    void process_req2resp_fifos();
    sc_core::sc_fifo<payload_type*> rd_resp_fifo{1}, wr_resp_fifo{1};
    void start_rd_resp_thread();
    void start_wr_resp_thread();
    sc_core::sc_fifo<std::tuple<fsm::fsm_handle*, axi::fsm::protocol_time_point_e>> wr_resp_beat_fifo{128}, rd_resp_beat_fifo{128};
    scc::ordered_semaphore rd_resp{1}, wr_resp_ch{1}, rd_resp_ch{1};
    void send_wr_resp_beat_thread();
    void send_rd_resp_beat_thread();
 
    sc_core::sc_clock* clk_if{nullptr};
    std::unique_ptr<bw_intor_impl> bw_intor;
    std::array<unsigned, 3> outstanding_cnt{{0, 0, 0}}; // count for limiting
    scc::sc_variable<unsigned> outstanding_rd_tx{"OutstandingRd", 0};
    scc::sc_variable<unsigned> outstanding_wr_tx{"OutstandingWr", 0};
    scc::sc_variable<unsigned> outstanding_ign_tx{"OutstandingIgn", 0};
    inline scc::sc_variable<unsigned>& getOutStandingTx(tlm::tlm_command cmd) {
        switch(cmd) {
        case tlm::TLM_READ_COMMAND:
            return outstanding_rd_tx;
        case tlm::TLM_WRITE_COMMAND:
            return outstanding_wr_tx;
        default:
            return outstanding_ign_tx;
        }
    }
    inline scc::sc_variable<unsigned> const& getOutStandingTx(tlm::tlm_command cmd) const {
        switch(cmd) {
        case tlm::TLM_READ_COMMAND:
            return outstanding_rd_tx;
        case tlm::TLM_WRITE_COMMAND:
            return outstanding_wr_tx;
        default:
            return outstanding_ign_tx;
        }
    }
    std::array<tlm::tlm_generic_payload*, 3> stalled_tx{nullptr, nullptr, nullptr};
    std::array<axi::fsm::protocol_time_point_e, 3> stalled_tp{{axi::fsm::CB_CNT, axi::fsm::CB_CNT, axi::fsm::CB_CNT}};
    void nb_fw(payload_type& trans, const phase_type& phase) {
        auto delay = sc_core::SC_ZERO_TIME;
        base::nb_fw(trans, phase, delay);
    }
    tlm_utils::peq_with_cb_and_phase<axi_target_pe> fw_peq{this, &axi_target_pe::nb_fw};
    std::unordered_set<unsigned> active_rdresp_id;
};
 
} // namespace pe
} // namespace axi