axi_lwtr.h

/*
 * Copyright 2023 Arteris IP
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
 
#pragma once
 
#include <array>
#include <axi/axi_tlm.h>
#include <axi/checker/axi_protocol.h>
#include <cci_configuration>
#include <regex>
#include <scc/peq.h>
#include <string>
#include <tlm/scc/lwtr/tlm2_lwtr.h>
#include <tlm/scc/tlm_mm.h>
#include <unordered_map>
#include <vector>

namespace axi {
namespace lwtr {
 
using tx_db = ::lwtr::tx_db;
using tx_fiber = ::lwtr::tx_fiber;
template <typename BEGIN, typename END> using tx_generator = ::lwtr::tx_generator<BEGIN, END>;
using tx_handle = ::lwtr::tx_handle;
using mm = tlm::scc::tlm_mm<>;
using namespace tlm::scc::lwtr;
 
extern bool registered;

template <typename TYPES = axi::axi_protocol_types>
class axi_lwtr : public virtual axi::axi_fw_transport_if<TYPES>, public virtual axi::axi_bw_transport_if<TYPES> {
public:
    cci::cci_param<bool> enableBlTracing;

    cci::cci_param<bool> enableNbTracing;

    cci::cci_param<bool> enableTimedTracing{"enableTimedTracing", true};

    cci::cci_param<bool> enableDmiTracing{"enableDmiTracing", false};

    cci::cci_param<bool> enableProtocolChecker{"enableProtocolChecker", false};
 
    cci::cci_param<unsigned> rd_response_timeout{"rd_response_timeout", 0};
 
    cci::cci_param<unsigned> wr_response_timeout{"wr_response_timeout", 0};

    axi_lwtr(char const* full_name, unsigned bus_width, bool recording_enabled = true, tx_db* tr_db = tx_db::get_default_db())
    : enableBlTracing("enableBlTracing", recording_enabled)
    , enableNbTracing("enableNbTracing", recording_enabled)
    , full_name(full_name)
    , nb_timed_peq()
    , bus_width(bus_width)
    , m_db(tr_db) {
        sc_core::sc_spawn_options opts;
        opts.spawn_method();
        opts.dont_initialize();
        opts.set_sensitivity(&nb_timed_peq.event());
        sc_core::sc_spawn([this]() { nbtx_cb(); }, nullptr, &opts);
        initialize_streams();
    }
 
    virtual ~axi_lwtr() override {
        nbtx_req_handle_map.clear();
        nbtx_last_req_handle_map.clear();
        nbtx_resp_handle_map.clear();
        nbtx_last_resp_handle_map.clear();
        delete checker;
        delete dmi_trInvalidateHandle;
        delete dmi_trGetHandle;
        delete dmi_streamHandle;
        for(auto* p : nb_trTimedHandle)
            delete p; // NOLINT
        delete nb_streamHandleTimed;
        for(auto* p : nb_trHandle)
            delete p; // NOLINT
        delete nb_streamHandle;
        for(auto* p : b_trTimedHandle)
            delete p; // NOLINT
        delete b_streamHandleTimed;
        for(auto* p : b_trHandle)
            delete p; // NOLINT
        delete b_streamHandle;
    }
 
    // TLM-2.0 interface methods for initiator and target sockets, surrounded with
    // Tx Recording
    tlm::tlm_sync_enum nb_transport_fw(typename TYPES::tlm_payload_type& trans, typename TYPES::tlm_phase_type& phase,
                                       sc_core::sc_time& delay) override;
    tlm::tlm_sync_enum nb_transport_bw(typename TYPES::tlm_payload_type& trans, typename TYPES::tlm_phase_type& phase,
                                       sc_core::sc_time& delay) override;
    void b_transport(typename TYPES::tlm_payload_type& trans, sc_core::sc_time& delay) override;
    bool get_direct_mem_ptr(typename TYPES::tlm_payload_type& trans, tlm::tlm_dmi& dmi_data) override;
    void invalidate_direct_mem_ptr(sc_dt::uint64 start_addr, sc_dt::uint64 end_addr) override;
    unsigned int transport_dbg(typename TYPES::tlm_payload_type& trans) override;
    inline bool isRecordingBlockingTxEnabled() const { return m_db && enableBlTracing.get_value(); }
    inline bool isRecordingNonBlockingTxEnabled() const { return m_db && enableNbTracing.get_value(); }
 
protected:
    sc_core::sc_port<axi::axi_fw_transport_if<TYPES>> fw_port{"fw_port"};

    sc_core::sc_port<axi::axi_bw_transport_if<TYPES>> bw_port{"bw_port"};
 
private:
    std::string const full_name;
    ::scc::peq<nb_rec_entry> nb_timed_peq;
    void nbtx_cb();
    const unsigned bus_width{0};
    tx_db* m_db{nullptr};
    ::lwtr::tx_relation_handle pred_succ_hndl{0}, par_chld_hndl{0};
    tx_fiber* b_streamHandle{nullptr};
    std::array<tx_generator<sc_core::sc_time, sc_core::sc_time>*, 3> b_trHandle{{nullptr, nullptr, nullptr}};
    tx_fiber* b_streamHandleTimed{nullptr};
    std::array<tx_generator<>*, 3> b_trTimedHandle{{nullptr, nullptr, nullptr}};
 
    enum DIR { FW, BW, REQ = FW, RESP = BW };
    tx_fiber* nb_streamHandle{nullptr};
    tx_fiber* nb_streamHandleTimed{nullptr};
    std::array<tx_generator<std::string, std::string>*, 2> nb_trHandle{{nullptr, nullptr}};
    std::array<tx_generator<>*, 2> nb_trTimedHandle{{nullptr, nullptr}};
    std::unordered_map<uint64_t, tx_handle> nbtx_req_handle_map;
    std::unordered_map<uint64_t, tx_handle> nbtx_last_req_handle_map;
    std::unordered_map<uint64_t, tx_handle> nbtx_resp_handle_map;
    std::unordered_map<uint64_t, tx_handle> nbtx_last_resp_handle_map;
    tx_fiber* dmi_streamHandle{nullptr};
    tx_generator<>* dmi_trGetHandle{nullptr};
    tx_generator<sc_dt::uint64, sc_dt::uint64>* dmi_trInvalidateHandle{nullptr};
 
protected:
    void initialize_streams() {
        if(m_db) {
            pred_succ_hndl = m_db->create_relation("PREDECESSOR_SUCCESSOR");
            par_chld_hndl = m_db->create_relation("PARENT_CHILD");
        }
        if(isRecordingBlockingTxEnabled() && !b_streamHandle) {
            b_streamHandle = new tx_fiber((full_name + "_bl").c_str(), "[TLM][axi][b]", m_db);
            b_trHandle[tlm::TLM_READ_COMMAND] =
                new tx_generator<sc_core::sc_time, sc_core::sc_time>("read", *b_streamHandle, "start_delay", "end_delay");
            b_trHandle[tlm::TLM_WRITE_COMMAND] =
                new tx_generator<sc_core::sc_time, sc_core::sc_time>("write", *b_streamHandle, "start_delay", "end_delay");
            b_trHandle[tlm::TLM_IGNORE_COMMAND] =
                new tx_generator<sc_core::sc_time, sc_core::sc_time>("ignore", *b_streamHandle, "start_delay", "end_delay");
            if(enableTimedTracing.get_value()) {
                b_streamHandleTimed = new tx_fiber((full_name + "_bl_timed").c_str(), "[TLM][axi][b][timed]", m_db);
                b_trTimedHandle[tlm::TLM_READ_COMMAND] = new tx_generator<>("read", *b_streamHandleTimed);
                b_trTimedHandle[tlm::TLM_WRITE_COMMAND] = new tx_generator<>("write", *b_streamHandleTimed);
                b_trTimedHandle[tlm::TLM_IGNORE_COMMAND] = new tx_generator<>("ignore", *b_streamHandleTimed);
            }
        }
        if(isRecordingNonBlockingTxEnabled() && !nb_streamHandle) {
            nb_streamHandle = new tx_fiber((full_name + "_nb").c_str(), "[TLM][axi][nb]", m_db);
            nb_trHandle[FW] = new tx_generator<std::string, std::string>("fw", *nb_streamHandle, "tlm_phase", "tlm_phase[return_path]");
            nb_trHandle[BW] = new tx_generator<std::string, std::string>("bw", *nb_streamHandle, "tlm_phase", "tlm_phase[return_path]");
            if(enableTimedTracing.get_value()) {
                nb_streamHandleTimed = new tx_fiber((full_name + "_nb_timed").c_str(), "[TLM][axi][nb][timed]", m_db);
                nb_trTimedHandle[FW] = new tx_generator<>("request", *nb_streamHandleTimed);
                nb_trTimedHandle[BW] = new tx_generator<>("response", *nb_streamHandleTimed);
            }
        }
        if(m_db && enableDmiTracing.get_value() && !dmi_streamHandle) {
            dmi_streamHandle = new tx_fiber((full_name + "_dmi").c_str(), "[TLM][axi][dmi]", m_db);
            dmi_trGetHandle = new tx_generator<>("get", *dmi_streamHandle);
            dmi_trInvalidateHandle =
                new tx_generator<sc_dt::uint64, sc_dt::uint64>("invalidate", *dmi_streamHandle, "start_addr", "end_addr");
        }
        if(enableProtocolChecker.get_value()) {
            checker =
                new axi::checker::axi_protocol(full_name, bus_width / 8, rd_response_timeout.get_value(), wr_response_timeout.get_value());
        }
    }
 
private:
    axi::checker::checker_if<TYPES>* checker{nullptr};
};
 
template <unsigned BUSWIDTH = 32, typename TYPES = axi::axi_protocol_types, int N = 1,
          sc_core::sc_port_policy POL = sc_core::SC_ONE_OR_MORE_BOUND>
class axi_lwtr_recorder : public sc_core::sc_module, public axi_lwtr<TYPES> {
public:
    axi::axi_target_socket<BUSWIDTH, TYPES, N, POL> ts{"ts"};
    axi::axi_initiator_socket<BUSWIDTH, TYPES, N, POL> is{"is"};
 
    axi_lwtr_recorder(sc_core::sc_module_name nm, bool recording_enabled = true, tx_db* tr_db = tx_db::get_default_db())
    : sc_core::sc_module(nm)
    , axi_lwtr<TYPES>(name(), BUSWIDTH, recording_enabled, tr_db) {
        is(*this);
        ts(*this);
        this->bw_port(ts.get_base_port());
        this->fw_port(is.get_base_port());
    }
};

// implementations of functions
 
template <typename TYPES> void axi_lwtr<TYPES>::b_transport(typename TYPES::tlm_payload_type& trans, sc_core::sc_time& delay) {
    if(!isRecordingBlockingTxEnabled()) {
        fw_port->b_transport(trans, delay);
        return;
    }
    // Get a handle for the new transaction
    tx_handle h = b_trHandle[trans.get_command()]->begin_tx(delay);
    tx_handle htim;
    /*************************************************************************
     * do the timed notification
     *************************************************************************/
    if(b_streamHandleTimed)
        htim = b_trTimedHandle[trans.get_command()]->begin_tx_delayed(sc_core::sc_time_stamp() + delay, par_chld_hndl, h);
 
    if(registered)
        for(auto& extensionRecording : lwtr4tlm2_extension_registry<TYPES>::inst().get())
            if(extensionRecording) {
                extensionRecording->recordBeginTx(h, trans);
                if(htim.is_valid())
                    extensionRecording->recordBeginTx(htim, trans);
            }
    link_pred_ext* preExt = nullptr;
 
    trans.get_extension(preExt);
    if(preExt == nullptr) { // we are the first recording this transaction
        preExt = new link_pred_ext(h, this);
        if(trans.has_mm())
            trans.set_auto_extension(preExt);
        else
            trans.set_extension(preExt);
    } else {
        h.add_relation(pred_succ_hndl, preExt->txHandle);
    }
    tx_handle preTx{preExt->txHandle};
    preExt->txHandle = h;
    fw_port->b_transport(trans, delay);
    trans.get_extension(preExt);
    if(preExt->creator == this) {
        // clean-up the extension if this is the original creator
        trans.set_extension(static_cast<link_pred_ext*>(nullptr));
        if(!trans.has_mm()) {
            delete preExt;
        }
    } else {
        preExt->txHandle = preTx;
    }
 
    h.record_attribute("trans", trans);
    if(registered)
        for(auto& extensionRecording : lwtr4tlm2_extension_registry<TYPES>::inst().get())
            if(extensionRecording) {
                extensionRecording->recordEndTx(h, trans);
                if(htim.is_active())
                    extensionRecording->recordEndTx(htim, trans);
            }
    // End the transaction
    h.end_tx(delay);
    // and now the stuff for the timed tx
    if(htim.is_valid()) {
        htim.record_attribute("trans", trans);
        htim.end_tx_delayed(sc_core::sc_time_stamp() + delay);
    }
}
 
template <typename TYPES>
tlm::tlm_sync_enum axi_lwtr<TYPES>::nb_transport_fw(typename TYPES::tlm_payload_type& trans, typename TYPES::tlm_phase_type& phase,
                                                    sc_core::sc_time& delay) {
    if(!isRecordingNonBlockingTxEnabled()) {
        if(checker) {
            checker->fw_pre(trans, phase);
            tlm::tlm_sync_enum status = fw_port->nb_transport_fw(trans, phase, delay);
            checker->fw_post(trans, phase, status);
            return status;
        } else
            return fw_port->nb_transport_fw(trans, phase, delay);
    }
    /*************************************************************************
     * prepare recording
     *************************************************************************/
    // Get a handle for the new transaction
    tx_handle h = nb_trHandle[FW]->begin_tx(phase.get_name());
    link_pred_ext* preExt = nullptr;
    trans.get_extension(preExt);
    if((phase == axi::BEGIN_PARTIAL_REQ || phase == tlm::BEGIN_REQ) && preExt == nullptr) { // we are the first recording this transaction
        preExt = new link_pred_ext(h, this);
        if(trans.has_mm())
            trans.set_auto_extension(preExt);
        else
            trans.set_extension(preExt);
    } else if(preExt != nullptr) {
        // link handle if we have a predecessor
        h.add_relation(pred_succ_hndl, preExt->txHandle);
    } else {
        sc_assert(preExt != nullptr && "ERROR on forward path in phase other than tlm::BEGIN_REQ");
    }
    // update the extension
    preExt->txHandle = h;
    h.record_attribute("delay", delay);
    if(registered)
        for(auto& extensionRecording : lwtr4tlm2_extension_registry<TYPES>::inst().get())
            if(extensionRecording)
                extensionRecording->recordBeginTx(h, trans);
    /*************************************************************************
     * do the timed notification
     *************************************************************************/
    if(nb_streamHandleTimed) {
        nb_rec_entry rec{mm::get().allocate(), phase, reinterpret_cast<uint64_t>(&trans), h};
        rec.tr->deep_copy_from(trans);
        nb_timed_peq.notify(rec, delay);
    }
    /*************************************************************************
     * do the access
     *************************************************************************/
    if(checker)
        checker->fw_pre(trans, phase);
    tlm::tlm_sync_enum status = fw_port->nb_transport_fw(trans, phase, delay);
    if(checker)
        checker->fw_post(trans, phase, status);
    /*************************************************************************
     * handle recording
     *************************************************************************/
    h.record_attribute("tlm_sync", status);
    h.record_attribute("delay[return_path]", delay);
    h.record_attribute("trans", trans);
    if(registered)
        for(auto& extensionRecording : lwtr4tlm2_extension_registry<TYPES>::inst().get())
            if(extensionRecording)
                extensionRecording->recordEndTx(h, trans);
    // get the extension and free the memory if it was mine
    if(status == tlm::TLM_COMPLETED || (status == tlm::TLM_ACCEPTED && phase == tlm::END_RESP)) {
        trans.get_extension(preExt);
        if(preExt && preExt->creator == this) {
            trans.set_extension(static_cast<link_pred_ext*>(nullptr));
            if(!trans.has_mm()) {
                delete preExt;
            }
        }
        /*************************************************************************
         * do the timed notification if req. finished here
         *************************************************************************/
        if(nb_streamHandleTimed) {
            nb_rec_entry rec{mm::get().allocate(), phase, reinterpret_cast<uint64_t>(&trans), h};
            rec.tr->deep_copy_from(trans);
            nb_timed_peq.notify(rec, delay);
        }
    } else if(nb_streamHandleTimed && status == tlm::TLM_UPDATED) {
        nb_rec_entry rec{mm::get().allocate(), phase, reinterpret_cast<uint64_t>(&trans), h};
        rec.tr->deep_copy_from(trans);
        nb_timed_peq.notify(rec, delay);
    }
    // End the transaction
    nb_trHandle[FW]->end_tx(h, phase.get_name());
    return status;
}
 
template <typename TYPES>
tlm::tlm_sync_enum axi_lwtr<TYPES>::nb_transport_bw(typename TYPES::tlm_payload_type& trans, typename TYPES::tlm_phase_type& phase,
                                                    sc_core::sc_time& delay) {
    if(!isRecordingNonBlockingTxEnabled()) {
        if(checker) {
            checker->bw_pre(trans, phase);
            tlm::tlm_sync_enum status = bw_port->nb_transport_bw(trans, phase, delay);
            checker->bw_post(trans, phase, status);
            return status;
        } else
            return bw_port->nb_transport_bw(trans, phase, delay);
    }
    /*************************************************************************
     * prepare recording
     *************************************************************************/
    link_pred_ext* preExt = nullptr;
    trans.get_extension(preExt);
    // Get a handle for the new transaction
    tx_handle h = nb_trHandle[BW]->begin_tx(phase.get_name());
    // link handle if we have a predecessor and that's not ourself
    if(phase == tlm::BEGIN_REQ && preExt == nullptr) { // we are the first recording this transaction
        preExt = new link_pred_ext(h, this);
        trans.set_extension(preExt);
        preExt->txHandle = h;
    } else if(preExt) {
        // link handle if we have a predecessor
        h.add_relation(pred_succ_hndl, preExt->txHandle);
        // and set the extension handle to this transaction
        preExt->txHandle = h;
    } else {
        sc_assert(preExt != nullptr && "ERROR on backward path in phase other than tlm::BEGIN_REQ");
    }
    // and set the extension handle to this transaction
    h.record_attribute("delay", delay);
    for(auto& extensionRecording : lwtr4tlm2_extension_registry<TYPES>::inst().get())
        if(extensionRecording)
            extensionRecording->recordBeginTx(h, trans);
    /*************************************************************************
     * do the timed notification
     *************************************************************************/
    if(nb_streamHandleTimed) {
        nb_rec_entry rec{mm::get().allocate(), phase, reinterpret_cast<uint64_t>(&trans), h};
        rec.tr->deep_copy_from(trans);
        nb_timed_peq.notify(rec, delay);
    }
    /*************************************************************************
     * do the access
     *************************************************************************/
    if(checker)
        checker->bw_pre(trans, phase);
    tlm::tlm_sync_enum status = bw_port->nb_transport_bw(trans, phase, delay);
    if(checker)
        checker->bw_post(trans, phase, status);
    /*************************************************************************
     * handle recording
     *************************************************************************/
    h.record_attribute("tlm_sync", status);
    h.record_attribute("delay[return_path]", delay);
    h.record_attribute("trans", trans);
    if(registered)
        for(auto& extensionRecording : lwtr4tlm2_extension_registry<TYPES>::inst().get())
            if(extensionRecording)
                extensionRecording->recordEndTx(h, trans);
    // End the transaction
    nb_trHandle[BW]->end_tx(h, phase.get_name());
    // get the extension and free the memory if it was mine
    if(status == tlm::TLM_COMPLETED || (status == tlm::TLM_UPDATED && phase == tlm::END_RESP)) {
        // the transaction is finished
        if(preExt && preExt->creator == this) {
            // clean-up the extension if this is the original creator
            trans.set_extension(static_cast<link_pred_ext*>(nullptr));
            if(!trans.has_mm()) {
                delete preExt;
            }
        }
        /*************************************************************************
         * do the timed notification if req. finished here
         *************************************************************************/
        if(nb_streamHandleTimed) {
            nb_rec_entry rec{mm::get().allocate(), phase, reinterpret_cast<uint64_t>(&trans), h};
            rec.tr->deep_copy_from(trans);
            nb_timed_peq.notify(rec, delay);
        }
    } else if(nb_streamHandleTimed && status == tlm::TLM_UPDATED) {
        nb_rec_entry rec{mm::get().allocate(), phase, reinterpret_cast<uint64_t>(&trans), h};
        rec.tr->deep_copy_from(trans);
        nb_timed_peq.notify(rec, delay);
    }
    return status;
}
 
template <typename TYPES> void axi_lwtr<TYPES>::nbtx_cb() {
    auto opt = nb_timed_peq.get_next();
    if(opt) {
        auto& e = opt.get();
        tx_handle h;
        // Now process outstanding recordings
        if(e.ph == tlm::BEGIN_REQ || e.ph == axi::BEGIN_PARTIAL_REQ) {
            h = nb_trTimedHandle[REQ]->begin_tx(par_chld_hndl, e.parent);
            nbtx_req_handle_map[e.id] = h;
        } else if(e.ph == tlm::END_REQ || e.ph == axi::END_PARTIAL_REQ) {
            auto it = nbtx_req_handle_map.find(e.id);
            if(it != nbtx_req_handle_map.end()) {
                h = it->second;
                nbtx_req_handle_map.erase(it);
                h.record_attribute("trans", *e.tr);
                h.end_tx();
                nbtx_last_req_handle_map[e.id] = h;
            }
        } else if(e.ph == tlm::BEGIN_RESP || e.ph == axi::BEGIN_PARTIAL_RESP) {
            auto it = nbtx_req_handle_map.find(e.id);
            if(it != nbtx_req_handle_map.end()) {
                h = it->second;
                nbtx_req_handle_map.erase(it);
                h.record_attribute("trans", *e.tr);
                h.end_tx();
                nbtx_last_req_handle_map[e.id] = h;
            }
            h = nb_trTimedHandle[RESP]->begin_tx(par_chld_hndl, e.parent);
            nbtx_resp_handle_map[e.id] = h;
            it = nbtx_last_req_handle_map.find(e.id);
            if(it != nbtx_last_req_handle_map.end()) {
                tx_handle& pred = it->second;
                h.add_relation(pred_succ_hndl, pred);
                nbtx_last_req_handle_map.erase(it);
            } else {
                it = nbtx_last_resp_handle_map.find(e.id);
                if(it != nbtx_last_resp_handle_map.end()) {
                    tx_handle& pred = it->second;
                    h.add_relation(pred_succ_hndl, pred);
                    nbtx_last_resp_handle_map.erase(it);
                }
            }
        } else if(e.ph == tlm::END_RESP || e.ph == axi::END_PARTIAL_RESP) {
            auto it = nbtx_resp_handle_map.find(e.id);
            if(it != nbtx_resp_handle_map.end()) {
                h = it->second;
                h.record_attribute("trans", *e.tr);
                nbtx_resp_handle_map.erase(it);
                h.end_tx();
                if(e.ph == axi::END_PARTIAL_RESP) {
                    nbtx_last_resp_handle_map[e.id] = h;
                }
            }
        } else
            sc_assert(!"phase not supported!");
    }
    return;
}
 
template <typename TYPES> bool axi_lwtr<TYPES>::get_direct_mem_ptr(typename TYPES::tlm_payload_type& trans, tlm::tlm_dmi& dmi_data) {
    if(!(m_db && enableDmiTracing.get_value()))
        return fw_port->get_direct_mem_ptr(trans, dmi_data);
    tx_handle h = dmi_trGetHandle->begin_tx();
    bool status = fw_port->get_direct_mem_ptr(trans, dmi_data);
    h.record_attribute("trans", trans);
    h.record_attribute("dmi_data", dmi_data);
    h.end_tx();
    return status;
}

template <typename TYPES> void axi_lwtr<TYPES>::invalidate_direct_mem_ptr(sc_dt::uint64 start_addr, sc_dt::uint64 end_addr) {
    if(!(m_db && enableDmiTracing.get_value())) {
        bw_port->invalidate_direct_mem_ptr(start_addr, end_addr);
        return;
    }
    tx_handle h = dmi_trInvalidateHandle->begin_tx(start_addr);
    bw_port->invalidate_direct_mem_ptr(start_addr, end_addr);
    dmi_trInvalidateHandle->end_tx(h, end_addr);
    return;
}

template <typename TYPES> unsigned int axi_lwtr<TYPES>::transport_dbg(typename TYPES::tlm_payload_type& trans) {
    return fw_port->transport_dbg(trans);
}
} // namespace lwtr
} // namespace axi