25 #ifndef __SCC_TLM_TARGET_BFS_H__
26 #define __SCC_TLM_TARGET_BFS_H__
28 #include "tlm_target.h"
30 #include <tlm_utils/simple_target_socket.h>
31 #include <util/ities.h>
35 #define ID_SCC_TLM_TARGET_BFS "scc: tlm target bitfield support"
40 uint64_t base_addr{0};
50 : base_addr(base_addr)
53 , num_regs(num_regs) {}
58 sc_core::sc_in<bool> rst_in_{
"reset_in"};
59 std::unique_ptr<std::vector<sc_core::sc_out<bool>>> irq_out_{
nullptr};
62 : params_{std::move(params)}
64 irq_out_ = util::make_unique<std::vector<sc_core::sc_out<bool>>>(params_.num_irqs);
68 const owner_t* getOwner()
const {
return owner_; }
70 void bindIRQ(
size_t num, sc_core::sc_signal<bool>* sig) {
71 if(num >= irq_out_->size()) {
72 SC_REPORT_FATAL(ID_SCC_TLM_TARGET_BFS,
"not enough IRQs in Per::connectIRQ()");
75 (*irq_out_)[num].bind(*sig);
80 owner_t*
const owner_{
nullptr};
90 template <
typename regs_t,
typename owner_t>
102 tlm::tlm_target_socket<LT>* get() noexcept {
return &parent.socket; }
111 : sc_core::sc_module{name}
114 , NAMEDD(regs, regs_t) {
115 regs->registerResources(*
this);
117 sensitive << rst_in_;
128 std::unique_ptr<regs_t> regs;
129 sc_core::sc_time clk;
Peripheral base class using scc::tlm_target.
socket_accessor sock_t_
The socket to access the memory mapped registers of this target.
a simple access-width based bus interface (no DMI support)