scc  2024.06
SystemC components library
axi_initiator.h
1 /*
2  * Copyright 2021 Arteris IP
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  * http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 #pragma once
18 
19 #include <axi/axi_tlm.h>
20 #include <axi/fsm/protocol_fsm.h>
21 #include <tlm/scc/pe/intor_if.h>
22 #include <scc/ordered_semaphore.h>
23 #include <scc/peq.h>
24 #include <scc/sc_variable.h>
25 #include <cci_configuration>
26 #include <systemc>
27 #include <tlm_utils/peq_with_get.h>
28 #include <tuple>
29 #include <unordered_map>
30 
31 namespace axi {
32 namespace pe {
33 
35  public sc_core::sc_module,
36  public axi::ace_bw_transport_if<axi::axi_protocol_types>,
38 {
39 public:
40 
41  using payload_type = axi::axi_protocol_types::tlm_payload_type;
42  using phase_type = axi::axi_protocol_types::tlm_phase_type;
43 
44  sc_core::sc_in<bool> clk_i{"clk_i"};
45 
46  sc_core::sc_export<tlm::scc::pe::intor_fw_b> fw_i{"fw_i"};
47 
48  sc_core::sc_port<tlm::scc::pe::intor_bw_b, 1, sc_core::SC_ZERO_OR_MORE_BOUND> bw_o{"bw_o"};
49 
50  void b_snoop(payload_type& trans, sc_core::sc_time& t) override;
51 
52  tlm::tlm_sync_enum nb_transport_bw(payload_type& trans, phase_type& phase, sc_core::sc_time& t) override;
53 
54  void invalidate_direct_mem_ptr(sc_dt::uint64 start_range, sc_dt::uint64 end_range) override;
55 
56  size_t get_transferwith_in_bytes() const { return transfer_width_in_bytes; }
66  void transport(payload_type& trans, bool blocking) override;
73  void snoop_resp(payload_type& trans, bool sync = false) override;
74 
75  axi_initiator_b(sc_core::sc_module_name nm, sc_core::sc_port_b<axi::axi_fw_transport_if<axi_protocol_types>>& port,
76  size_t transfer_width, flavor_e flavor);
77 
78  virtual ~axi_initiator_b();
79 
80  axi_initiator_b() = delete;
81 
82  axi_initiator_b(axi_initiator_b const&) = delete;
83 
84  axi_initiator_b(axi_initiator_b&&) = delete;
85 
86  axi_initiator_b& operator=(axi_initiator_b const&) = delete;
87 
88  axi_initiator_b& operator=(axi_initiator_b&&) = delete;
89 
90  // AXI4 does not allow write data interleaving, and ncore3 only supports AXI4.
91  // However, AXI3 allows data interleaving and there may be support for AXI3 in Symphony, so keep it configurable in
92  // the testbench.
93  cci::cci_param<bool> data_interleaving{"data_interleaving", false};
95  cci::cci_param<unsigned> artv{"artv", 1};
97  cci::cci_param<unsigned> awtv{"awtv", 1};
99  cci::cci_param<unsigned> wbv{"wbv", 1};
101  cci::cci_param<unsigned> rbr{"rbr", 0};
103  cci::cci_param<unsigned> br{"br", 0};
105  cci::cci_param<unsigned> rla{"rla", 1};
107  cci::cci_param<unsigned> ba{"ba", 1};
109  cci::cci_param<bool> enable_id_serializing{"enable_id_serializing", false};
111  cci::cci_param<unsigned> outstanding_snoops{"outstanding_snoops", 8};
112 
122  void add_protocol_cb(axi::fsm::protocol_time_point_e e, std::function<void(payload_type&, bool)> cb) {
123  assert(e < axi::fsm::CB_CNT);
124  protocol_cb[e] = cb;
125  }
126 
127 
128 protected:
129  unsigned calculate_beats(payload_type& p) {
130  sc_assert(p.get_data_length() > 0);
131  return p.get_data_length() < transfer_width_in_bytes ? 1 : p.get_data_length() / transfer_width_in_bytes;
132  }
133 
134  void snoop_thread();
135 
136  const size_t transfer_width_in_bytes;
137 
138  const flavor_e flavor;
139 
140  sc_core::sc_port_b<axi::axi_fw_transport_if<axi_protocol_types>>& socket_fw;
141 
142  struct tx_state {
143  payload_type* active_tx{nullptr};
145  };
146  std::unordered_map<void*, tx_state*> tx_state_by_tx;
147  std::unordered_map<unsigned, scc::ordered_semaphore*> id_mtx;
148 
149  tlm_utils::peq_with_get<payload_type> snp_peq{"snp_peq"};
150 
151  std::unordered_map<void*, tx_state*> snp_state_by_id;
152 
153  scc::ordered_semaphore rd_chnl{1};
154 
155  scc::ordered_semaphore wr_chnl{1};
156 
157  scc::ordered_semaphore sresp_chnl{1};
158 
159  sc_core::sc_event any_tx_finished;
160 
161  sc_core::sc_time clk_period{10, sc_core::SC_NS};
162 
163  scc::sc_variable<unsigned> rd_waiting{"RdWaiting", 0};
164  scc::sc_variable<unsigned> wr_waiting{"WrWaiting", 0};
165  scc::sc_variable<unsigned> rd_outstanding{"RdOutstanding", 0};
166  scc::sc_variable<unsigned> wr_outstanding{"WrOutstanding", 0};
167 
168 private:
169  sc_core::sc_clock* clk_if{nullptr};
170  void end_of_elaboration() override;
171  void clk_counter() { m_clock_counter++; }
172  unsigned get_clk_cnt() { return m_clock_counter; }
173 
174  tlm::tlm_phase send(payload_type& trans, axi::pe::axi_initiator_b::tx_state* txs, tlm::tlm_phase phase);
175 
176  unsigned m_clock_counter{0};
177  unsigned m_prev_clk_cnt{0};
178  unsigned snoops_in_flight{0};
179 
180  std::array<std::function<void(payload_type&, bool)>, axi::fsm::CB_CNT> protocol_cb;
181 };
182 
186 template <unsigned int BUSWIDTH = 32, typename TYPES = axi::axi_protocol_types, int N = 1,
187  sc_core::sc_port_policy POL = sc_core::SC_ONE_OR_MORE_BOUND>
189 public:
190  using base = axi_initiator_b;
191 
192  using payload_type = base::payload_type;
193  using phase_type = base::phase_type;
198  axi_initiator(const sc_core::sc_module_name& nm, axi::axi_initiator_socket<BUSWIDTH, TYPES, N, POL>& socket_)
199  : axi_initiator_b(nm, socket_.get_base_port(), BUSWIDTH, flavor_e::AXI)
200  , socket(socket_) {
201  socket(*this);
202  }
203 
204  axi_initiator() = delete;
205 
206  axi_initiator(axi_initiator const&) = delete;
207 
208  axi_initiator(axi_initiator&&) = delete;
209 
210  axi_initiator& operator=(axi_initiator const&) = delete;
211 
212  axi_initiator& operator=(axi_initiator&&) = delete;
213 
214 private:
216 };
217 
221 template <unsigned int BUSWIDTH = 32, typename TYPES = axi::axi_protocol_types, int N = 1,
222  sc_core::sc_port_policy POL = sc_core::SC_ONE_OR_MORE_BOUND>
224 public:
225  using base = axi_initiator_b;
226 
227  using payload_type = base::payload_type;
228  using phase_type = base::phase_type;
233  ace_lite_initiator(const sc_core::sc_module_name& nm, axi::axi_initiator_socket<BUSWIDTH, TYPES, N, POL>& socket_)
234  : axi_initiator_b(nm, socket_.get_base_port(), BUSWIDTH, flavor_e::ACEL)
235  , socket(socket_) {
236  socket(*this);
237  }
238 
239  ace_lite_initiator() = delete;
240 
241  ace_lite_initiator(ace_lite_initiator const&) = delete;
242 
244 
245  ace_lite_initiator& operator=(ace_lite_initiator const&) = delete;
246 
247  ace_lite_initiator& operator=(ace_lite_initiator&&) = delete;
248 
249 private:
251 };
252 
256 template <unsigned int BUSWIDTH = 32, typename TYPES = axi::axi_protocol_types, int N = 1,
257  sc_core::sc_port_policy POL = sc_core::SC_ONE_OR_MORE_BOUND>
259 public:
260  using base = axi_initiator_b;
261 
262  using payload_type = base::payload_type;
263  using phase_type = base::phase_type;
268  ace_initiator(const sc_core::sc_module_name& nm, axi::ace_initiator_socket<BUSWIDTH, TYPES, N, POL>& socket_)
269  : axi_initiator_b(nm, socket_.get_base_port(), BUSWIDTH, flavor_e::ACE)
270  , socket(socket_) {
271  socket(*this);
272  }
273 
274  ace_initiator() = delete;
275 
276  ace_initiator(ace_initiator const&) = delete;
277 
278  ace_initiator(ace_initiator&&) = delete;
279 
280  ace_initiator& operator=(ace_initiator const&) = delete;
281 
282  ace_initiator& operator=(ace_initiator&&) = delete;
283 
284 private:
286 };
287 
288 } /* namespace pe */
289 } /* namespace axi */
ace_initiator(const sc_core::sc_module_name &nm, axi::ace_initiator_socket< BUSWIDTH, TYPES, N, POL > &socket_)
the constructor
ace_lite_initiator(const sc_core::sc_module_name &nm, axi::axi_initiator_socket< BUSWIDTH, TYPES, N, POL > &socket_)
the constructor
cci::cci_param< unsigned > rla
Read last data handshake to acknowledge.
cci::cci_param< unsigned > wbv
Write data handshake to next beat valid.
Definition: axi_initiator.h:99
cci::cci_param< unsigned > br
Write response valid to ready.
void snoop_resp(payload_type &trans, bool sync=false) override
triggers a non-blocking snoop response if the snoop callback does not do so.
cci::cci_param< unsigned > outstanding_snoops
number of snoops which can be handled
void add_protocol_cb(axi::fsm::protocol_time_point_e e, std::function< void(payload_type &, bool)> cb)
register a callback for a certain time point
cci::cci_param< unsigned > ba
Write response handshake to acknowledge.
cci::cci_param< unsigned > rbr
Read data valid to same beat ready.
cci::cci_param< unsigned > artv
Read address valid to next read address valid.
Definition: axi_initiator.h:95
void transport(payload_type &trans, bool blocking) override
The forward transport function. It behaves blocking and is re-entrant.
cci::cci_param< unsigned > awtv
Write address valid to next write address valid.
Definition: axi_initiator.h:97
cci::cci_param< bool > enable_id_serializing
Quirks enable.
axi_initiator(const sc_core::sc_module_name &nm, axi::axi_initiator_socket< BUSWIDTH, TYPES, N, POL > &socket_)
the constructor
The ordered_semaphore primitive channel class.
TLM2.0 components modeling AHB.
Definition: axi_initiator.h:30
tlm::tlm_fw_transport_if< TYPES > axi_fw_transport_if
alias declaration for the forward interface
Definition: axi_tlm.h:954
The AXI protocol traits class. Since the protocoll defines additional non-ignorable phases a dedicate...
Definition: axi_tlm.h:920
priority event queue
Definition: peq.h:41