21 #include <boost/mpl/list.hpp>
22 #include <boost/statechart/custom_reaction.hpp>
23 #include <boost/statechart/event.hpp>
24 #include <boost/statechart/state.hpp>
25 #include <boost/statechart/state_machine.hpp>
26 #include <boost/statechart/transition.hpp>
30 namespace mpl = boost::mpl;
31 namespace bsc = boost::statechart;
36 struct WReq : bsc::event<WReq> {};
39 struct BegReq : bsc::event<BegReq> {};
40 struct EndReq : bsc::event<EndReq> {};
62 void InvokeResponsePhaseBeg(
const BegResp&) {
63 if(cb.at(axi::fsm::ResponsePhaseBeg))
64 cb.at(axi::fsm::ResponsePhaseBeg)();
67 if(cb.at(axi::fsm::ResponsePhaseBeg))
68 cb.at(axi::fsm::ResponsePhaseBeg)();
71 for(
auto& f:cb) f=
nullptr;
72 bsc::state_machine<AxiProtocolFsm, Idle>::terminate();
74 axi::fsm::protocol_cb cb;
77 struct Idle : bsc::state<Idle, AxiProtocolFsm> {
81 if(context<AxiProtocolFsm>().cb.at(axi::fsm::RequestPhaseBeg))
82 context<AxiProtocolFsm>().cb.at(axi::fsm::RequestPhaseBeg)();
84 typedef mpl::list<bsc::transition<BegPartReq, PartialRequest>, bsc::transition<BegReq, Request>,
85 bsc::transition<WReq, ATrans>>
90 : bsc::state<ATrans, AxiProtocolFsm> {
93 if(context<AxiProtocolFsm>().cb.at(axi::fsm::WValidE))
94 context<AxiProtocolFsm>().cb.at(axi::fsm::WValidE)();
97 if(context<AxiProtocolFsm>().cb.at(axi::fsm::WReadyE))
98 context<AxiProtocolFsm>().cb.at(axi::fsm::WReadyE)();
100 typedef mpl::list<bsc::transition<BegPartReq, PartialRequest>, bsc::transition<BegReq, Request>> reactions;
104 : bsc::state<PartialRequest, AxiProtocolFsm> {
107 if(context<AxiProtocolFsm>().cb.at(axi::fsm::BegPartReqE))
108 context<AxiProtocolFsm>().cb.at(axi::fsm::BegPartReqE)();
111 if(context<AxiProtocolFsm>().cb.at(axi::fsm::EndPartReqE))
112 context<AxiProtocolFsm>().cb.at(axi::fsm::EndPartReqE)();
114 typedef bsc::transition<EndPartReq, WriteIdle> reactions;
118 : bsc::simple_state<WriteIdle, AxiProtocolFsm> {
119 typedef mpl::list<bsc::transition<BegPartReq, PartialRequest>, bsc::transition<BegReq, Request>> reactions;
123 : bsc::state<Request, AxiProtocolFsm> {
126 if(context<AxiProtocolFsm>().cb.at(axi::fsm::BegReqE))
127 context<AxiProtocolFsm>().cb.at(axi::fsm::BegReqE)();
130 if(context<AxiProtocolFsm>().cb.at(axi::fsm::EndReqE))
131 context<AxiProtocolFsm>().cb.at(axi::fsm::EndReqE)();
134 bsc::transition<EndReq, WaitForResponse>,
135 bsc::transition<BegResp, Response, AxiProtocolFsm, &AxiProtocolFsm::InvokeResponsePhaseBeg>,
136 bsc::transition<BegPartResp, PartialResponse, AxiProtocolFsm, &AxiProtocolFsm::InvokeResponsePhaseBeg>>
141 : bsc::state<WaitForResponse, AxiProtocolFsm> {
145 if(context<AxiProtocolFsm>().cb.at(axi::fsm::ResponsePhaseBeg))
146 context<AxiProtocolFsm>().cb.at(axi::fsm::ResponsePhaseBeg)();
148 typedef mpl::list<bsc::transition<BegPartResp, PartialResponse>, bsc::transition<BegResp, Response>> reactions;
152 : bsc::state<PartialResponse, AxiProtocolFsm> {
155 if(context<AxiProtocolFsm>().cb.at(axi::fsm::BegPartRespE))
156 context<AxiProtocolFsm>().cb.at(axi::fsm::BegPartRespE)();
159 if(context<AxiProtocolFsm>().cb.at(axi::fsm::EndPartRespE))
160 context<AxiProtocolFsm>().cb.at(axi::fsm::EndPartRespE)();
162 typedef bsc::transition<EndPartResp, ReadIdle> reactions;
166 : bsc::simple_state<ReadIdle, AxiProtocolFsm> {
167 typedef mpl::list<bsc::transition<BegPartResp, PartialResponse>, bsc::transition<BegResp, Response>> reactions;
171 : bsc::state<Response, AxiProtocolFsm> {
174 if(context<AxiProtocolFsm>().cb.at(axi::fsm::BegRespE))
175 context<AxiProtocolFsm>().cb.at(axi::fsm::BegRespE)();
178 if(context<AxiProtocolFsm>().cb.at(axi::fsm::EndRespE))
179 context<AxiProtocolFsm>().cb.at(axi::fsm::EndRespE)();
181 typedef mpl::list<bsc::transition<EndResp, Idle>, bsc::transition<EndRespNoAck, WaitAck>> reactions;
185 : bsc::state<WaitAck, AxiProtocolFsm> {
189 if(context<AxiProtocolFsm>().cb.at(axi::fsm::Ack))
190 context<AxiProtocolFsm>().cb.at(axi::fsm::Ack)();
192 typedef bsc::transition<AckRecv, Idle> reactions;
TLM2.0 components modeling AHB.
special state to map AWREADY/WDATA of SNPS to AXI protocol
the beat of a burst response
the phase between 2 read burst response beats
the request, either the last beat of a write or the address phase of a read
the write response or the last read response (beat)
waiting for ack in case of ACE access
the operation state where the target can do it's stuff
the phase between 2 burst beats, should keep the link locked