17 #ifndef _BUS_AHB_PIN_TARGET_H_
18 #define _BUS_AHB_PIN_TARGET_H_
21 #include <tlm/scc/initiator_mixin.h>
23 #include <tlm_utils/peq_with_get.h>
30 template <
unsigned DWIDTH,
unsigned AWIDTH>
class target : sc_core::sc_module {
31 static constexpr
bool is_larger(
unsigned x) {
return x > 64U; }
32 using addr_t =
typename std::conditional<is_larger(AWIDTH), sc_dt::sc_biguint<AWIDTH>, sc_dt::sc_uint<AWIDTH>>::type;
33 using data_t =
typename std::conditional<is_larger(DWIDTH), sc_dt::sc_biguint<DWIDTH>, sc_dt::sc_uint<DWIDTH>>::type;
36 sc_core::sc_in<bool> HCLK_i{
"HCLK_i"};
37 sc_core::sc_in<bool> HRESETn_i{
"HRESETn_i"};
38 sc_core::sc_in<addr_t> HADDR_i{
"HADDR_i"};
39 sc_core::sc_in<sc_dt::sc_uint<3>> HBURST_i{
"HBURST_i"};
40 sc_core::sc_in<bool> HMASTLOCK_i{
"HMASTLOCK_i"};
41 sc_core::sc_in<sc_dt::sc_uint<4>> HPROT_i{
"HPROT_i"};
42 sc_core::sc_in<sc_dt::sc_uint<3>> HSIZE_i{
"HSIZE_i"};
43 sc_core::sc_in<sc_dt::sc_uint<2>> HTRANS_i{
"HTRANS_i"};
44 sc_core::sc_in<data_t> HWDATA_i{
"HWDATA_i"};
45 sc_core::sc_in<bool> HWRITE_i{
"HWRITE_i"};
46 sc_core::sc_in<bool> HSEL_i{
"HSEL_i"};
47 sc_core::sc_out<data_t> HRDATA_o{
"HRDATA_o"};
48 sc_core::sc_out<bool> HREADY_o{
"HREADY_o"};
49 sc_core::sc_out<bool> HRESP_o{
"HRESP_o"};
53 target(
const sc_core::sc_module_name& nm);
59 static tlm::tlm_generic_payload* wait4tx(tlm_utils::peq_with_get<tlm::tlm_generic_payload>& que) {
60 tlm::tlm_generic_payload* ret = que.get_next_transaction();
62 ::sc_core::wait(que.get_event());
63 ret = que.get_next_transaction();
67 sc_core::sc_event end_req_evt;
68 tlm_utils::peq_with_get<tlm::tlm_generic_payload> resp_que{
"resp_que"};
69 tlm_utils::peq_with_get<tlm::tlm_generic_payload> tx_in_flight{
"tx_in_flight"};
70 bool waiting4end_req{
false};
TLM2.0 components modeling AHB.