scc 2026.07
SystemC components library
axi_ace_lwtr.cpp
1/*
2 * Copyright 2020 Arteris IP
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include <axi/axi_tlm.h>
18#include <tlm/scc/lwtr/lwtr4tlm2_extension_registry.h>
19#include <tlm/scc/scv/tlm_extension_recording_registry.h>
20#include <tlm/scc/tlm_id.h>
21
22namespace lwtr {
23template <class Archive> void record(Archive& ar, tlm::scc::tlm_id_extension const& e) { ar& field("uid", e.id); }
24template <class Archive> void record(Archive& ar, axi::axi3_extension const& e) {
25 ar& field("id", e.get_id());
26 ar& field("user[CTRL]", e.get_user(axi::common::id_type::CTRL));
27 ar& field("user[DATA]", e.get_user(axi::common::id_type::DATA));
28 ar& field("user[RESP]", e.get_user(axi::common::id_type::RESP));
29 ar& field("length", e.get_length());
30 ar& field("size", e.get_size());
31 ar& field("burst", to_char(e.get_burst()));
32 ar& field("prot", e.get_prot());
33 ar& field("exclusive", e.is_exclusive() ? "true" : "false");
34 ar& field("cache", e.get_cache());
35 ar& field("cache_bufferable", e.is_bufferable());
36 ar& field("cache_cacheable", e.is_cacheable());
37 ar& field("cache_read_alloc", e.is_read_allocate());
38 ar& field("cache_write_alloc", e.is_write_allocate());
39 ar& field("qos", e.get_qos());
40 ar& field("region", e.get_region());
41}
42
43template <class Archive> void record(Archive& ar, axi::axi4_extension const& e) {
44 ar& field("id", e.get_id());
45 ar& field("user[CTRL]", e.get_user(axi::common::id_type::CTRL));
46 ar& field("user[DATA]", e.get_user(axi::common::id_type::DATA));
47 ar& field("user[RESP]", e.get_user(axi::common::id_type::RESP));
48 ar& field("length", e.get_length());
49 ar& field("size", e.get_size());
50 ar& field("burst", to_char(e.get_burst()));
51 ar& field("prot", e.get_prot());
52 ar& field("exclusive", e.is_exclusive() ? "true" : "false");
53 ar& field("cache", e.get_cache());
54 ar& field("cache_bufferable", e.is_bufferable());
55 ar& field("cache_modifiable", e.is_modifiable());
56 ar& field("cache_allocate", e.is_allocate());
57 ar& field("cache_other_alloc", e.is_other_allocate());
58 ar& field("qos", e.get_qos());
59 ar& field("region", e.get_region());
60}
61
62template <class Archive> void record(Archive& ar, axi::ace_extension const& e) {
63 ar& field("id", e.get_id());
64 ar& field("user[CTRL]", e.get_user(axi::common::id_type::CTRL));
65 ar& field("user[DATA]", e.get_user(axi::common::id_type::DATA));
66 ar& field("user[RESP]", e.get_user(axi::common::id_type::RESP));
67 ar& field("length", e.get_length());
68 ar& field("size", e.get_size());
69 ar& field("burst", to_char(e.get_burst()));
70 ar& field("prot", e.get_prot());
71 ar& field("exclusive", e.is_exclusive() ? "true" : "false");
72 ar& field("cache", e.get_cache());
73 ar& field("cache_bufferable", e.is_bufferable());
74 ar& field("cache_modifiable", e.is_modifiable());
75 ar& field("cache_write_alloc", e.is_write_allocate());
76 ar& field("cache_read_alloc", e.is_read_allocate());
77 ar& field("qos", e.get_qos());
78 ar& field("region", e.get_region());
79 ar& field("domain", to_char(e.get_domain()));
80 ar& field("snoop", to_char(e.get_snoop()));
81 ar& field("barrier", to_char(e.get_barrier()));
82 ar& field("unique", e.get_unique());
83}
84
85} // namespace lwtr
86
87namespace axi {
88namespace lwtr {
89namespace {
90const std::array<std::string, 3> cmd2char{{"tlm::TLM_READ_COMMAND", "tlm::TLM_WRITE_COMMAND", "tlm::TLM_IGNORE_COMMAND"}};
91const std::array<std::string, 7> resp2char{{"tlm::TLM_OK_RESPONSE", "tlm::TLM_INCOMPLETE_RESPONSE", "tlm::TLM_GENERIC_ERROR_RESPONSE",
92 "tlm::TLM_ADDRESS_ERROR_RESPONSE", "tlm::TLM_COMMAND_ERROR_RESPONSE",
93 "tlm::TLM_BURST_ERROR_RESPONSE", "tlm::TLM_BYTE_ENABLE_ERROR_RESPONSE"}};
94const std::array<std::string, 3> gp_option2char{{"tlm::TLM_MIN_PAYLOAD", "tlm::TLM_FULL_PAYLOAD", "tlm::TLM_FULL_PAYLOAD_ACCEPTED"}};
95const std::array<std::string, 5> phase2char{
96 {"tlm::UNINITIALIZED_PHASE", "tlm::BEGIN_REQ", "tlm::END_REQ", "tlm::BEGIN_RESP", "tlm::END_RESP"}};
97const std::array<std::string, 4> dmi2char{
98 {"tlm::DMI_ACCESS_NONE", "tlm::DMI_ACCESS_READ", "tlm::DMI_ACCESS_WRITE", "tlm::DMI_ACCESS_READ_WRITE"}};
99const std::array<std::string, 3> sync2char{{"tlm::TLM_ACCEPTED", "tlm::TLM_UPDATED", "tlm::TLM_COMPLETED"}};
100} // namespace
101
103 void recordBeginTx(::lwtr::tx_handle& handle, tlm::tlm_base_protocol_types::tlm_payload_type& trans) override {
104 if(auto* ext = trans.get_extension<tlm::scc::tlm_id_extension>())
105 handle.record_attribute("trans", *ext);
106 }
107 void recordEndTx(::lwtr::tx_handle& handle, tlm::tlm_base_protocol_types::tlm_payload_type& trans) override {}
108};
109
111 void recordBeginTx(::lwtr::tx_handle& handle, axi_protocol_types::tlm_payload_type& trans) override {
112 if(auto* ext = trans.get_extension<axi3_extension>())
113 handle.record_attribute("trans.axi3", *ext);
114 }
115 void recordEndTx(::lwtr::tx_handle& handle, axi_protocol_types::tlm_payload_type& trans) override {
116 if(auto* ext = trans.get_extension<axi3_extension>())
117 handle.record_attribute("trans.axi3.resp", to_char(ext->get_resp()));
118 }
119};
120
122 void recordBeginTx(::lwtr::tx_handle& handle, axi_protocol_types::tlm_payload_type& trans) override {
123 if(auto* ext = trans.get_extension<axi4_extension>())
124 handle.record_attribute("trans.axi4", *ext);
125 }
126 void recordEndTx(::lwtr::tx_handle& handle, axi_protocol_types::tlm_payload_type& trans) override {
127 if(auto* ext = trans.get_extension<axi4_extension>())
128 handle.record_attribute("trans.axi4.resp", to_char(ext->get_resp()));
129 }
130};
131
133 void recordBeginTx(::lwtr::tx_handle& handle, axi_protocol_types::tlm_payload_type& trans) override {
134 if(auto* ext = trans.get_extension<ace_extension>())
135 handle.record_attribute("trans.ace", *ext);
136 }
137 void recordEndTx(::lwtr::tx_handle& handle, axi_protocol_types::tlm_payload_type& trans) override {
138 if(auto* ext = trans.get_extension<ace_extension>()) {
139 handle.record_attribute("trans.ace.resp", to_char(ext->get_resp()));
140 handle.record_attribute("trans.ace.cresp_PassDirty", ext->is_pass_dirty());
141 handle.record_attribute("trans.ace.cresp_IsShared", ext->is_shared());
142 handle.record_attribute("trans.ace.cresp_SnoopDataTransfer", ext->is_snoop_data_transfer());
143 handle.record_attribute("trans.ace.cresp_SnoopError", ext->is_snoop_error());
144 handle.record_attribute("trans.ace.cresp_SnoopWasUnique", ext->is_snoop_was_unique());
145 }
146 }
147};
148
149// using namespace tlm::scc::scv;
150#if defined(__GNUG__)
151__attribute__((constructor))
152#endif
153bool register_extensions() {
154 tlm::scc::tlm_id_extension ext(nullptr); // NOLINT
155 tlm::scc::lwtr::lwtr4tlm2_extension_registry<axi::axi_protocol_types>::inst().register_ext_rec(
156 ext.ID, new axi::lwtr::tlm_id_ext_recording()); // NOLINT
157 axi::axi3_extension ext3; // NOLINT
158 tlm::scc::lwtr::lwtr4tlm2_extension_registry<axi::axi_protocol_types>::inst().register_ext_rec(
159 ext3.ID, new axi::lwtr::axi3_ext_recording()); // NOLINT
160 axi::axi4_extension ext4; // NOLINT
161 tlm::scc::lwtr::lwtr4tlm2_extension_registry<axi::axi_protocol_types>::inst().register_ext_rec(
162 ext4.ID, new axi::lwtr::axi4_ext_recording()); // NOLINT
163 axi::ace_extension extace; // NOLINT
164 tlm::scc::lwtr::lwtr4tlm2_extension_registry<axi::axi_protocol_types>::inst().register_ext_rec(
165 extace.ID, new axi::lwtr::ace_ext_recording()); // NOLINT
166 return true; // NOLINT
167}
168bool registered = register_extensions();
169
170} // namespace lwtr
171} // namespace axi
The TLM transaction extensions recorder interface.
TLM2.0 components modeling AHB.
const char * to_char(E t)
const char * to_char(E t)
bool get_unique() const
get the AxUNIQUE value return the unique value
Definition axi_tlm.h:1513
bar_e get_barrier() const
get the AxBAR value return the barrier value
Definition axi_tlm.h:1509
snoop_e get_snoop() const
get the AxSNOOP value return the snoop value
Definition axi_tlm.h:1505
domain_e get_domain() const
get the AxDOMAIN value return the domain value
Definition axi_tlm.h:1501
bool is_bufferable() const
get the bufferable bit of AxCACHE (AxCACHE[0]) return the bufferable bit
Definition axi_tlm.h:1326
bool is_read_allocate() const
get the read_allocate bit of AxCACHE (AxCACHE[3]) return the read_allocate bit
Definition axi_tlm.h:1353
bool is_exclusive() const
get the exclusive bit of AxLOCK (AxLOCK[0]) return the exclusive bit
Definition axi_tlm.h:1300
bool is_write_allocate() const
get the write_allocate bit of AxCACHE (AxCACHE[2]) return the write_allocate bit
Definition axi_tlm.h:1344
bool is_cacheable() const
get the cacheable bit of AxCACHE (AxCACHE[1]) return the cacheable bit
Definition axi_tlm.h:1335
bool is_modifiable() const
get the modifiable bit of AxCACHE (AxCACHE[1]) return the modifiable bit
Definition axi_tlm.h:1375
bool is_allocate() const
get the write allocate/read other allocate bit of AxCACHE (AxCACHE[3]) return the write_other_allocat...
Definition axi_tlm.h:1384
bool is_bufferable() const
get the bufferable bit of AxCACHE (AxCACHE[0]) return the bufferable bit
Definition axi_tlm.h:1366
bool is_exclusive() const
get the exclusive bit of AxLOCK (AxLOCK[0]) return the exclusive bit
Definition axi_tlm.h:1357
bool is_write_allocate() const
get the write allocate/read other allocate bit of AxCACHE (AxCACHE[3]) return the write_other_allocat...
Definition axi_tlm.h:1411
bool is_read_allocate() const
get the read allocate/write other allocate bit of AxCACHE (AxCACHE[2]) return the read_other_allocate...
Definition axi_tlm.h:1420
bool is_other_allocate() const
get the read allocate/write other allocate bit of AxCACHE (AxCACHE[2]) return the read_other_allocate...
Definition axi_tlm.h:1393
unsigned int get_user(id_type chnl) const
Definition axi_tlm.h:1289
unsigned int get_id() const
Definition axi_tlm.h:1285
burst_e get_burst() const
get the AxBURST value,
Definition axi_tlm.h:1451
uint8_t get_length() const
get the AxLEN value of the transaction, the value denotes the burst length - 1
Definition axi_tlm.h:1440
uint8_t get_region() const
get the AxREGION value
Definition axi_tlm.h:1490
uint8_t get_qos() const
get the AxQOS (quality of service) value
Definition axi_tlm.h:1486
uint8_t get_cache() const
get the AxCACHE value as POD
Definition axi_tlm.h:1497
uint8_t get_prot() const
set the AxPROT value as POD, only values from 0...7 are allowed
Definition axi_tlm.h:1458
uint8_t get_size() const
set the AxSIZE value of the transaction
Definition axi_tlm.h:1447