| axi_lwtr(char const *full_name, unsigned bus_width, bool recording_enabled=true, tx_db *tr_db=tx_db::get_default_db()) | axi::lwtr::axi_lwtr< TYPES > | inline |
| b_transport(typename TYPES::tlm_payload_type &trans, sc_core::sc_time &delay) override | axi::lwtr::axi_lwtr< TYPES > | |
| bw_port | axi::lwtr::axi_lwtr< TYPES > | protected |
| enableBlTracing | axi::lwtr::axi_lwtr< TYPES > | |
| enableDmiTracing | axi::lwtr::axi_lwtr< TYPES > | |
| enableNbTracing | axi::lwtr::axi_lwtr< TYPES > | |
| enableProtocolChecker | axi::lwtr::axi_lwtr< TYPES > | |
| enableTimedTracing | axi::lwtr::axi_lwtr< TYPES > | |
| fw_port | axi::lwtr::axi_lwtr< TYPES > | protected |
| get_direct_mem_ptr(typename TYPES::tlm_payload_type &trans, tlm::tlm_dmi &dmi_data) override | axi::lwtr::axi_lwtr< TYPES > | |
| initialize_streams() (defined in axi::lwtr::axi_lwtr< TYPES >) | axi::lwtr::axi_lwtr< TYPES > | inlineprotected |
| invalidate_direct_mem_ptr(sc_dt::uint64 start_addr, sc_dt::uint64 end_addr) override | axi::lwtr::axi_lwtr< TYPES > | |
| isRecordingBlockingTxEnabled() const | axi::lwtr::axi_lwtr< TYPES > | inline |
| isRecordingNonBlockingTxEnabled() const | axi::lwtr::axi_lwtr< TYPES > | inline |
| nb_transport_bw(typename TYPES::tlm_payload_type &trans, typename TYPES::tlm_phase_type &phase, sc_core::sc_time &delay) override | axi::lwtr::axi_lwtr< TYPES > | |
| nb_transport_fw(typename TYPES::tlm_payload_type &trans, typename TYPES::tlm_phase_type &phase, sc_core::sc_time &delay) override | axi::lwtr::axi_lwtr< TYPES > | |
| rd_response_timeout (defined in axi::lwtr::axi_lwtr< TYPES >) | axi::lwtr::axi_lwtr< TYPES > | |
| transport_dbg(typename TYPES::tlm_payload_type &trans) override | axi::lwtr::axi_lwtr< TYPES > | |
| wr_response_timeout (defined in axi::lwtr::axi_lwtr< TYPES >) | axi::lwtr::axi_lwtr< TYPES > | |
| ~axi_lwtr() override (defined in axi::lwtr::axi_lwtr< TYPES >) | axi::lwtr::axi_lwtr< TYPES > | inlinevirtual |