recorder_modules.h

/*
 * Copyright 2020 Arteris IP
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
 
#pragma once
 
#include <chi/scv/chi_recorder.h>
 
namespace chi {
namespace scv {
template <unsigned int BUSWIDTH, typename TYPES, typename BASE> class chitlm_recorder_module : public sc_core::sc_module, public BASE {
public:
    typename BASE::template target_socket_type<BUSWIDTH> tsckt{"tsckt"};
    typename BASE::template initiator_socket_type<BUSWIDTH> isckt{"isckt"};

    chitlm_recorder_module(sc_core::sc_module_name name, bool recording_enabled = true,
                           SCVNS scv_tr_db* tr_db = SCVNS scv_tr_db::get_default_db())
    : sc_module(name)
    , BASE(sc_core::sc_object::name(), recording_enabled, tr_db) {
        // bind the sockets to the module
        tsckt.bind(*this);
        isckt.bind(*this);
    }
 
    virtual ~chitlm_recorder_module() {}
 
    tlm::tlm_fw_transport_if<TYPES>* get_fw_if() override { return isckt.get_base_port().operator->(); }
 
    tlm::tlm_bw_transport_if<TYPES>* get_bw_if() override { return tsckt.get_base_port().operator->(); }
 
private:
    void start_of_simulation() override { BASE::initialize_streams(); }
};
 
template <unsigned int BUSWIDTH = 32>
using chi_trx_recorder_module = chitlm_recorder_module<BUSWIDTH, chi::chi_protocol_types, chi_trx_recorder<chi::chi_protocol_types>>;
 
} // namespace scv
} // namespace chi