scc 2026.07
SystemC components library
ace_protocol.cpp
1/*
2 * Copyright 2020-2022 Arteris IP
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include <axi/checker/ace_protocol.h>
18#include <scc/report.h>
19namespace axi {
20namespace checker {
21
22ace_protocol::~ace_protocol() = default;
23
24void ace_protocol::fw_pre(const ace_protocol::payload_type& trans, const ace_protocol::phase_type& phase) {
25 auto cmd = trans.get_command();
26 if(cmd == tlm::TLM_IGNORE_COMMAND)
27 SCCERR(name) << "Illegal command: tlm::TLM_IGNORE_COMMAND on forward path";
28 if(check_phase_change(trans, phase))
29#ifndef NCSC
30 SCCERR(name) << "Illegal phase transition: " << phase.get_name() << " on forward path";
31#else
32 SCCERR(name) << "Illegal phase transition: " << phase << " on return in forward path";
33#endif
34}
35
36void ace_protocol::fw_post(const ace_protocol::payload_type& trans, const ace_protocol::phase_type& phase, tlm::tlm_sync_enum rstat) {
37 if(rstat == tlm::TLM_ACCEPTED)
38 return;
39 auto cmd = trans.get_command();
40 if(req_beat[cmd] == tlm::BEGIN_REQ && (phase == tlm::BEGIN_RESP || phase == axi::BEGIN_PARTIAL_RESP))
41 req_beat[cmd] = tlm::UNINITIALIZED_PHASE;
42 if(check_phase_change(trans, phase))
43#ifndef NCSC
44 SCCERR(name) << "Illegal phase transition: " << phase.get_name() << " on return in forward path";
45#else
46 SCCERR(name) << "Illegal phase transition: " << phase << " on return in forward path";
47#endif
48}
49
50void ace_protocol::bw_pre(const ace_protocol::payload_type& trans, const ace_protocol::phase_type& phase) {
51 auto cmd = trans.get_command();
52 if(cmd == tlm::TLM_IGNORE_COMMAND)
53 SCCERR(name) << "Illegal command: tlm::TLM_IGNORE_COMMAND on forward path";
54 if(check_phase_change(trans, phase))
55#ifndef NCSC
56 SCCERR(name) << "Illegal phase transition: " << phase.get_name() << " on backward path";
57#else
58 SCCERR(name) << "Illegal phase transition: " << phase << " on backward path";
59#endif
60}
61
62void ace_protocol::bw_post(const ace_protocol::payload_type& trans, const ace_protocol::phase_type& phase, tlm::tlm_sync_enum rstat) {
63 if(rstat == tlm::TLM_ACCEPTED)
64 return;
65 if(check_phase_change(trans, phase))
66#ifndef NCSC
67 SCCERR(name) << "Illegal phase transition: " << phase.get_name() << " on return in backward path";
68#else
69 SCCERR(name) << "Illegal phase transition: " << phase << " on forward path";
70#endif
71}
72
73bool ace_protocol::check_phase_change(payload_type const& trans, const ace_protocol::phase_type& phase) {
74 // phase tests
75 auto cur_req = req_beat[trans.get_command()];
76 auto cur_resp = resp_beat[trans.get_command()];
77 bool error{false};
78 if(phase == tlm::BEGIN_REQ || phase == axi::BEGIN_PARTIAL_REQ) {
79 error |= cur_req != tlm::UNINITIALIZED_PHASE;
80 cur_req = phase;
81 } else if(phase == axi::END_PARTIAL_REQ) {
82 error |= cur_req != axi::BEGIN_PARTIAL_REQ;
83 cur_req = tlm::UNINITIALIZED_PHASE;
84 } else if(phase == tlm::END_REQ) {
85 error |= cur_req != tlm::BEGIN_REQ;
86 cur_req = tlm::UNINITIALIZED_PHASE;
87 } else if(phase == tlm::BEGIN_RESP || phase == axi::BEGIN_PARTIAL_RESP) {
88 error |= cur_resp != tlm::UNINITIALIZED_PHASE;
89 cur_resp = phase;
90 } else if(phase == tlm::END_RESP) {
91 error |= cur_resp != tlm::BEGIN_RESP;
92 cur_resp = tlm::UNINITIALIZED_PHASE;
93 } else if(phase == axi::END_PARTIAL_RESP) {
94 error |= cur_resp != axi::BEGIN_PARTIAL_RESP;
95 cur_resp = tlm::UNINITIALIZED_PHASE;
96 } else {
97 error |= true;
98 }
99 if(req_beat[trans.get_command()] != cur_req) {
100 req_beat[trans.get_command()] = cur_req;
101 request_update(trans);
102 }
103 if(resp_beat[trans.get_command()] != cur_resp) {
104 resp_beat[trans.get_command()] = cur_resp;
105 response_update(trans);
106 }
107 return error;
108}
109
110void ace_protocol::request_update(const payload_type& trans) {
111 auto axi_id = axi::get_axi_id(trans);
112 auto axi_burst_len = axi::get_burst_length(trans);
113 auto axi_burst_size = axi::get_burst_size(trans);
114 if(trans.is_write()) {
115 if(req_beat[tlm::TLM_WRITE_COMMAND] == tlm::UNINITIALIZED_PHASE) {
116 req_id[tlm::TLM_WRITE_COMMAND] = umax;
117 } else {
118 if(req_id[tlm::TLM_WRITE_COMMAND] == umax) {
119 req_id[tlm::TLM_WRITE_COMMAND] = axi_id;
120 wr_req_beat_count++;
121 } else if(req_id[tlm::TLM_WRITE_COMMAND] != axi_id) {
122 SCCERR(name) << "Illegal ordering: a transaction with AWID:0x" << std::hex << axi_id
123 << " starts while a transaction with AWID:0x" << req_id[tlm::TLM_WRITE_COMMAND] << " is active";
124 }
125 if(req_beat[tlm::TLM_WRITE_COMMAND] == tlm::BEGIN_REQ) {
126 if(wr_req_beat_count != axi_burst_len) {
127 SCCERR(name) << "Illegal AXI settings: number of transferred beats (" << wr_req_beat_count
128 << ") does not comply with AWLEN:0x" << std::hex << axi::get_burst_length(trans) - 1;
129 }
130 auto mask = bw - 1ULL;
131 auto offset = trans.get_address() & mask;
132 if(!offset) {
133 if(trans.get_data_length() > (1 << axi_burst_size) * axi_burst_len) {
134 SCCERR(name) << "Illegal AXI settings: transaction data length (" << trans.get_data_length()
135 << ") does not correspond to AxSIZE/AxLEN setting (" << axi_burst_size << "/" << axi_burst_len - 1
136 << ") for " << trans;
137 }
138 } else {
139 if((trans.get_data_length() + offset) >= (1 << axi_burst_size) * axi_burst_len) {
140 SCCERR(name) << "Illegal AXI settings: transaction data length (" << trans.get_data_length()
141 << ") does not correspond to AxSIZE/AxLEN setting (" << axi_burst_size << "/" << axi_burst_len - 1
142 << ") for " << trans;
143 }
144 }
145 wr_req_beat_count = 0;
146 open_tx_by_id[tlm::TLM_WRITE_COMMAND][axi_id].push_back(reinterpret_cast<uintptr_t>(&trans));
147 }
148 check_properties(trans);
149 }
150 } else if(trans.is_read()) {
151 if(req_beat[tlm::TLM_READ_COMMAND] == tlm::UNINITIALIZED_PHASE) {
152 req_id[tlm::TLM_READ_COMMAND] = umax;
153 } else if(req_beat[tlm::TLM_READ_COMMAND] == tlm::BEGIN_REQ) {
154 if(req_id[tlm::TLM_READ_COMMAND] == umax) {
155 req_id[tlm::TLM_READ_COMMAND] = axi_id;
156 open_tx_by_id[tlm::TLM_READ_COMMAND][axi_id].push_back(reinterpret_cast<uintptr_t>(&trans));
157 } else if(req_id[tlm::TLM_READ_COMMAND] != axi_id) {
158 SCCERR(name) << "Illegal phase: a read transaction uses a phase with id " << req_beat[tlm::TLM_READ_COMMAND];
159 }
160 check_properties(trans);
161 } else {
162 SCCERR(name) << "Illegal phase: a read transaction uses a phase with id " << req_beat[tlm::TLM_READ_COMMAND];
163 }
164 }
165}
166
167void ace_protocol::response_update(const payload_type& trans) {
168 auto axi_id = axi::get_axi_id(trans);
169 auto axi_burst_len = axi::get_burst_length(trans);
170 auto axi_burst_size = axi::get_burst_size(trans);
171 if(trans.is_write()) {
172 if(resp_beat[tlm::TLM_WRITE_COMMAND] == tlm::UNINITIALIZED_PHASE) {
173 resp_id[tlm::TLM_WRITE_COMMAND] = umax;
174 } else if(resp_beat[tlm::TLM_WRITE_COMMAND] == tlm::BEGIN_RESP) {
175 if(resp_id[tlm::TLM_WRITE_COMMAND] == umax) {
176 resp_id[tlm::TLM_WRITE_COMMAND] = axi_id;
177 if(open_tx_by_id[tlm::TLM_WRITE_COMMAND][axi_id].front() != reinterpret_cast<uintptr_t>(&trans)) {
178 SCCERR(name) << "Write response ordering violation: a response with AWID:0x" << std::hex << axi_id
179 << " starts before the previous response with the same id finished";
180 }
181 } else if(resp_id[tlm::TLM_WRITE_COMMAND] != axi_id) {
182 SCCERR(name) << "Illegal phase: a read transaction uses a phase with id " << resp_beat[tlm::TLM_WRITE_COMMAND];
183 }
184 open_tx_by_id[tlm::TLM_WRITE_COMMAND][axi_id].pop_front();
185 } else {
186 SCCERR(name) << "Illegal phase: a read transaction uses a phase with id " << resp_beat[tlm::TLM_WRITE_COMMAND];
187 }
188 } else if(trans.is_read()) {
189 if(resp_beat[tlm::TLM_READ_COMMAND] == tlm::UNINITIALIZED_PHASE) {
190 resp_id[tlm::TLM_READ_COMMAND] = umax;
191 } else {
192 if(resp_id[tlm::TLM_READ_COMMAND] == umax) {
193 resp_id[tlm::TLM_READ_COMMAND] = axi_id;
194 if(open_tx_by_id[tlm::TLM_READ_COMMAND][axi_id].front() != reinterpret_cast<uintptr_t>(&trans)) {
195 SCCERR(name) << "Read response ordering violation: a response with ARID:0x" << std::hex << axi_id
196 << " starts before the previous response with the same id finished";
197 }
198 rd_resp_beat_count[axi_id]++;
199 } else if(resp_id[tlm::TLM_READ_COMMAND] != axi_id) {
200 SCCERR(name) << "Illegal phase: a read transaction uses a phase with id " << resp_beat[tlm::TLM_READ_COMMAND];
201 }
202 if(resp_beat[tlm::TLM_READ_COMMAND] == tlm::BEGIN_RESP) {
203 if(rd_resp_beat_count[axi_id] != axi_burst_len) {
204 SCCERR(name) << "Illegal AXI settings: number of transferred beats (" << wr_req_beat_count
205 << ") does not comply with AWLEN:0x" << std::hex << axi::get_burst_length(trans) - 1;
206 }
207 auto mask = bw - 1ULL;
208 auto offset = trans.get_address() & mask;
209 if(!offset) {
210 if(trans.get_data_length() > (1 << axi_burst_size) * axi_burst_len) {
211 SCCERR(name) << "Illegal AXI settings: transaction data length (" << trans.get_data_length()
212 << ") does not correspond to AxSIZE/AxLEN setting (" << axi_burst_size << "/" << axi_burst_len - 1
213 << ") for " << trans;
214 }
215 } else {
216 if((trans.get_data_length() + offset) >= (1 << axi_burst_size) * axi_burst_len) {
217 SCCERR(name) << "Illegal AXI settings: transaction data length (" << trans.get_data_length()
218 << ") does not correspond to AxSIZE/AxLEN setting (" << axi_burst_size << "/" << axi_burst_len - 1
219 << ") for " << trans;
220 }
221 }
222 open_tx_by_id[tlm::TLM_READ_COMMAND][axi_id].pop_front();
223 rd_resp_beat_count[axi_id] = 0;
224 }
225 }
226 }
227}
228
229constexpr unsigned comb(axi::bar_e bar, axi::domain_e domain, axi::snoop_e snoop) {
230 return to_int(bar) << 10 | to_int(domain) << 8 | to_int(snoop);
231};
232
233void ace_protocol::check_properties(const payload_type& trans) {
234 if(auto* ace_ext = trans.get_extension<axi::ace_extension>()) {
235 if(ace_ext->get_cache() & 0xc0) {
236 if(!ace_ext->get_cache())
237 SCCERR(name) << "Illegal ACEL settings: active allocate bit(s) requires modifiable bit set";
238 }
239 auto snoop = ace_ext->get_snoop();
240 auto domain = ace_ext->get_domain();
241 auto bar = ace_ext->get_barrier();
242 switch(comb(bar, domain, snoop)) {
243 // Non-snooping
244 case comb(bar_e::RESPECT_BARRIER, domain_e::NON_SHAREABLE, snoop_e::READ_NO_SNOOP):
245 case comb(bar_e::RESPECT_BARRIER, domain_e::SYSTEM, snoop_e::READ_NO_SNOOP):
246 // Coherent
247 case comb(bar_e::RESPECT_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::READ_ONCE):
248 case comb(bar_e::RESPECT_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::READ_ONCE):
249 case comb(bar_e::RESPECT_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::READ_SHARED):
250 case comb(bar_e::RESPECT_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::READ_SHARED):
251 case comb(bar_e::RESPECT_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::READ_CLEAN):
252 case comb(bar_e::RESPECT_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::READ_CLEAN):
253 case comb(bar_e::RESPECT_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::READ_NOT_SHARED_DIRTY):
254 case comb(bar_e::RESPECT_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::READ_NOT_SHARED_DIRTY):
255 case comb(bar_e::RESPECT_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::READ_UNIQUE):
256 case comb(bar_e::RESPECT_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::READ_UNIQUE):
257 case comb(bar_e::RESPECT_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::CLEAN_UNIQUE):
258 case comb(bar_e::RESPECT_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::CLEAN_UNIQUE):
259 case comb(bar_e::RESPECT_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::MAKE_UNIQUE):
260 case comb(bar_e::RESPECT_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::MAKE_UNIQUE):
261 // Cache maintenance
262 case comb(bar_e::RESPECT_BARRIER, domain_e::NON_SHAREABLE, snoop_e::CLEAN_SHARED):
263 case comb(bar_e::RESPECT_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::CLEAN_SHARED):
264 case comb(bar_e::RESPECT_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::CLEAN_SHARED):
265 case comb(bar_e::RESPECT_BARRIER, domain_e::NON_SHAREABLE, snoop_e::CLEAN_INVALID):
266 case comb(bar_e::RESPECT_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::CLEAN_INVALID):
267 case comb(bar_e::RESPECT_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::CLEAN_INVALID):
268 case comb(bar_e::RESPECT_BARRIER, domain_e::NON_SHAREABLE, snoop_e::MAKE_INVALID):
269 case comb(bar_e::RESPECT_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::MAKE_INVALID):
270 case comb(bar_e::RESPECT_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::MAKE_INVALID):
271 // Barrier
272 case comb(bar_e::MEMORY_BARRIER, domain_e::NON_SHAREABLE, snoop_e::READ_NO_SNOOP):
273 case comb(bar_e::MEMORY_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::READ_ONCE):
274 case comb(bar_e::MEMORY_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::READ_ONCE):
275 case comb(bar_e::MEMORY_BARRIER, domain_e::SYSTEM, snoop_e::READ_NO_SNOOP):
276 // Non-snooping
277 case comb(bar_e::RESPECT_BARRIER, domain_e::NON_SHAREABLE, snoop_e::WRITE_NO_SNOOP):
278 case comb(bar_e::RESPECT_BARRIER, domain_e::SYSTEM, snoop_e::WRITE_NO_SNOOP):
279 // Coherent
280 case comb(bar_e::RESPECT_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::WRITE_UNIQUE):
281 case comb(bar_e::RESPECT_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::WRITE_UNIQUE):
282 case comb(bar_e::RESPECT_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::WRITE_LINE_UNIQUE):
283 case comb(bar_e::RESPECT_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::WRITE_LINE_UNIQUE):
284 // Memory update
285 case comb(bar_e::MEMORY_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::WRITE_CLEAN):
286 case comb(bar_e::MEMORY_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::WRITE_CLEAN):
287 case comb(bar_e::MEMORY_BARRIER, domain_e::SYSTEM, snoop_e::WRITE_CLEAN):
288 case comb(bar_e::MEMORY_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::WRITE_BACK):
289 case comb(bar_e::MEMORY_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::WRITE_BACK):
290 case comb(bar_e::MEMORY_BARRIER, domain_e::SYSTEM, snoop_e::WRITE_BACK):
291 case comb(bar_e::MEMORY_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::EVICT):
292 case comb(bar_e::MEMORY_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::EVICT):
293 case comb(bar_e::MEMORY_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::WRITE_EVICT):
294 case comb(bar_e::MEMORY_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::WRITE_EVICT):
295 case comb(bar_e::MEMORY_BARRIER, domain_e::SYSTEM, snoop_e::WRITE_EVICT):
296 // Barrier
297 case comb(bar_e::MEMORY_BARRIER, domain_e::NON_SHAREABLE, snoop_e::WRITE_NO_SNOOP):
298 case comb(bar_e::MEMORY_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::WRITE_UNIQUE):
299 case comb(bar_e::MEMORY_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::WRITE_UNIQUE):
300 case comb(bar_e::MEMORY_BARRIER, domain_e::SYSTEM, snoop_e::WRITE_NO_SNOOP):
301 break;
302 default:
303 SCCERR(name) << "Illegal ACE settings: According to D3.1.1 Read and write Shareable transaction types of ARM IHI 0022H the "
304 "following setting is illegal:\n"
305 << "AxBAR:" << to_char(bar) << ", AxDOMAIN:" << to_char(domain) << ", AxSNOOP:" << to_char(snoop);
306 }
307 switch(snoop) {
308 default:
309 break;
310 case snoop_e::READ_CLEAN:
311 case snoop_e::READ_NOT_SHARED_DIRTY:
312 case snoop_e::READ_SHARED:
313 case snoop_e::READ_UNIQUE:
314 case snoop_e::CLEAN_UNIQUE:
315 case snoop_e::MAKE_UNIQUE:
316 case snoop_e::WRITE_LINE_UNIQUE:
317 case snoop_e::EVICT:
318 if(ace_ext->get_domain() == domain_e::NON_SHAREABLE) {
319 SCCERR(name) << "Illegal ACE settings: According to D3.1.6 Transaction constraints of ARM IHI 0022H the following setting "
320 "is illegal:\n"
321 << "AxDOMAIN:" << to_char(ace_ext->get_domain());
322 }
323 /* no break */
324 case snoop_e::CLEAN_SHARED:
325 case snoop_e::CLEAN_INVALID:
326 case snoop_e::MAKE_INVALID:
327 case snoop_e::WRITE_EVICT:
328 if(ace_ext->get_domain() == domain_e::SYSTEM) {
329 SCCERR(name) << "Illegal ACE settings: According to D3.1.6 Transaction constraints of ARM IHI 0022H the following setting "
330 "is illegal:\n"
331 << "AxDOMAIN:" << to_char(ace_ext->get_domain());
332 }
333 if(ace_ext->get_length() && (1u << ace_ext->get_size()) != bw) {
334 SCCERR(name) << "Illegal ACE settings: According to D3.1.6 Transaction constraints of ARM IHI 0022H the following setting "
335 "is illegal:\n"
336 << "AxLEN:" << static_cast<unsigned>(ace_ext->get_length())
337 << ", AxSIZE:" << static_cast<unsigned>(ace_ext->get_size()) << " with bus with:" << bw;
338 }
339 auto width = bw;
340 switch(ace_ext->get_burst()) {
341 case burst_e::INCR:
342 width = (1 + ace_ext->get_length()) * (1u << ace_ext->get_size());
343 /* no break */
344 case burst_e::WRAP:
345 if(trans.get_address() & (width - 1)) {
346 SCCERR(name) << "Illegal ACE settings: According to D3.1.6 Transaction constraints of ARM IHI 0022H the following "
347 "setting is illegal:\n"
348 << "AxBURST:" << to_char(ace_ext->get_burst()) << ", ADDR:0x" << std::hex << trans.get_address();
349 }
350 break;
351 case burst_e::FIXED:
352 SCCERR(name) << "Illegal ACE settings: According to D3.1.6 Transaction constraints of ARM IHI 0022H the following setting "
353 "is illegal:\n"
354 << "AxBURST:" << to_char(ace_ext->get_burst());
355 }
356 if(ace_ext->get_barrier() != bar_e::IGNORE_BARRIER) {
357 SCCERR(name) << "Illegal ACE settings: According to D3.1.6 Transaction constraints of ARM IHI 0022H the following setting "
358 "is illegal:\n"
359 << "AxBAR:" << to_char(ace_ext->get_barrier());
360 }
361 if(!ace_ext->is_modifiable()) {
362 SCCERR(name) << "Illegal ACE settings: According to D3.1.6 Transaction constraints of ARM IHI 0022H the following setting "
363 "is illegal:\n"
364 << "AxCACHE:" << static_cast<unsigned>(ace_ext->get_cache());
365 }
366 }
367 }
368}
369
370} /* namespace checker */
371} /* namespace axi */
axi
TLM2.0 components modeling AHB.
Definition axi_initiator.h:30
axi::to_char
const char * to_char(E t)
axi::get_burst_length
unsigned get_burst_length(const request &r)
Definition axi_tlm.h:1157
axi::domain_e
domain_e
Definition axi_tlm.h:84
axi::bar_e
bar_e
Definition axi_tlm.h:88
axi::bar_e::MEMORY_BARRIER
@ MEMORY_BARRIER
Normal access, respecting barriers.
Definition axi_tlm.h:90
axi::bar_e::IGNORE_BARRIER
@ IGNORE_BARRIER
Memory barrier.
Definition axi_tlm.h:91
axi::snoop_e
snoop_e
Definition axi_tlm.h:98
axi::to_int
constexpr ULT to_int(E t)
Definition axi_tlm.h:46
axi::get_burst_size
unsigned get_burst_size(const request &r)
Definition axi_tlm.h:1190