scc 2025.09
SystemC components library
ace_protocol.cpp
1/*
2 * Copyright 2020-2022 Arteris IP
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include <axi/checker/ace_protocol.h>
18#include <scc/report.h>
19namespace axi {
20namespace checker {
21
22ace_protocol::~ace_protocol() = default;
23
24void ace_protocol::fw_pre(const ace_protocol::payload_type &trans, const ace_protocol::phase_type &phase) {
25 auto cmd = trans.get_command();
26 if (cmd == tlm::TLM_IGNORE_COMMAND)
27 SCCERR(name) << "Illegal command: tlm::TLM_IGNORE_COMMAND on forward path";
28 if (check_phase_change(trans, phase))
29#ifndef NCSC
30 SCCERR(name) << "Illegal phase transition: " << phase.get_name() << " on forward path";
31#else
32 SCCERR(name) << "Illegal phase transition: " << phase << " on return in forward path";
33#endif
34}
35
36void ace_protocol::fw_post(const ace_protocol::payload_type &trans, const ace_protocol::phase_type &phase, tlm::tlm_sync_enum rstat) {
37 if(rstat == tlm::TLM_ACCEPTED) return;
38 auto cmd = trans.get_command();
39 if(req_beat[cmd]==tlm::BEGIN_REQ && (phase == tlm::BEGIN_RESP || phase == axi::BEGIN_PARTIAL_RESP))
40 req_beat[cmd]= tlm::UNINITIALIZED_PHASE;
41 if (check_phase_change(trans, phase))
42#ifndef NCSC
43 SCCERR(name) << "Illegal phase transition: " << phase.get_name() << " on return in forward path";
44#else
45 SCCERR(name) << "Illegal phase transition: " << phase << " on return in forward path";
46#endif
47}
48
49void ace_protocol::bw_pre(const ace_protocol::payload_type &trans, const ace_protocol::phase_type &phase) {
50 auto cmd = trans.get_command();
51 if (cmd == tlm::TLM_IGNORE_COMMAND)
52 SCCERR(name) << "Illegal command: tlm::TLM_IGNORE_COMMAND on forward path";
53 if (check_phase_change(trans, phase))
54#ifndef NCSC
55 SCCERR(name) << "Illegal phase transition: " << phase.get_name() << " on backward path";
56#else
57 SCCERR(name) << "Illegal phase transition: " << phase << " on backward path";
58#endif
59}
60
61void ace_protocol::bw_post(const ace_protocol::payload_type &trans, const ace_protocol::phase_type &phase, tlm::tlm_sync_enum rstat) {
62 if(rstat == tlm::TLM_ACCEPTED) return;
63 if (check_phase_change(trans, phase))
64#ifndef NCSC
65 SCCERR(name) << "Illegal phase transition: " << phase.get_name() << " on return in backward path";
66#else
67 SCCERR(name) << "Illegal phase transition: " << phase << " on forward path";
68#endif
69}
70
71bool ace_protocol::check_phase_change(payload_type const& trans, const ace_protocol::phase_type &phase) {
72 // phase tests
73 auto cur_req = req_beat[trans.get_command()];
74 auto cur_resp = resp_beat[trans.get_command()];
75 bool error{false};
76 if (phase == tlm::BEGIN_REQ || phase == axi::BEGIN_PARTIAL_REQ) {
77 error |= cur_req != tlm::UNINITIALIZED_PHASE;
78 cur_req = phase;
79 } else if(phase==axi::END_PARTIAL_REQ) {
80 error |= cur_req != axi::BEGIN_PARTIAL_REQ;
81 cur_req = tlm::UNINITIALIZED_PHASE;
82 } else if(phase==tlm::END_REQ) {
83 error |= cur_req != tlm::BEGIN_REQ;
84 cur_req = tlm::UNINITIALIZED_PHASE;
85 } else if(phase == tlm::BEGIN_RESP || phase == axi::BEGIN_PARTIAL_RESP) {
86 error |= cur_resp!=tlm::UNINITIALIZED_PHASE;
87 cur_resp = phase;
88 } else if (phase == tlm::END_RESP) {
89 error |= cur_resp != tlm::BEGIN_RESP;
90 cur_resp = tlm::UNINITIALIZED_PHASE;
91 } else if (phase == axi::END_PARTIAL_RESP) {
92 error |= cur_resp != axi::BEGIN_PARTIAL_RESP;
93 cur_resp = tlm::UNINITIALIZED_PHASE;
94 } else {
95 error |= true;
96 }
97 if(req_beat[trans.get_command()] != cur_req){
98 req_beat[trans.get_command()] = cur_req;
99 request_update(trans);
100 }
101 if(resp_beat[trans.get_command()] != cur_resp){
102 resp_beat[trans.get_command()] = cur_resp;
103 response_update(trans);
104 }
105 return error;
106}
107
108void ace_protocol::request_update(const payload_type &trans) {
109 auto axi_id = axi::get_axi_id(trans);
110 auto axi_burst_len = axi::get_burst_length(trans);
111 auto axi_burst_size = axi::get_burst_size(trans);
112 if(trans.is_write()){
113 if(req_beat[tlm::TLM_WRITE_COMMAND]==tlm::UNINITIALIZED_PHASE) {
114 req_id[tlm::TLM_WRITE_COMMAND] = umax;
115 } else {
116 if(req_id[tlm::TLM_WRITE_COMMAND] == umax) {
117 req_id[tlm::TLM_WRITE_COMMAND] = axi_id;
118 wr_req_beat_count++;
119 } else if(req_id[tlm::TLM_WRITE_COMMAND] != axi_id){
120 SCCERR(name) << "Illegal ordering: a transaction with AWID:0x"<<std::hex<<axi_id<<" starts while a transaction with AWID:0x"<<req_id[tlm::TLM_WRITE_COMMAND]<<" is active";
121 }
122 if(req_beat[tlm::TLM_WRITE_COMMAND]==tlm::BEGIN_REQ) {
123 if(wr_req_beat_count != axi_burst_len){
124 SCCERR(name) << "Illegal AXI settings: number of transferred beats ("<<wr_req_beat_count<<") does not comply with AWLEN:0x"<<std::hex<<axi::get_burst_length(trans)-1;
125 }
126 auto mask = bw-1ULL;
127 auto offset = trans.get_address() & mask;
128 if(!offset){
129 if(trans.get_data_length() > (1 << axi_burst_size) * axi_burst_len) {
130 SCCERR(name) << "Illegal AXI settings: transaction data length (" << trans.get_data_length() << ") does not correspond to AxSIZE/AxLEN setting ("
131 << axi_burst_size << "/" << axi_burst_len-1 << ") for " << trans;
132 }
133 } else {
134 if((trans.get_data_length() + offset) >= (1 << axi_burst_size) * axi_burst_len) {
135 SCCERR(name) << "Illegal AXI settings: transaction data length (" << trans.get_data_length() << ") does not correspond to AxSIZE/AxLEN setting ("
136 << axi_burst_size << "/" << axi_burst_len-1 << ") for " << trans;
137 }
138 }
139 wr_req_beat_count=0;
140 open_tx_by_id[tlm::TLM_WRITE_COMMAND][axi_id].push_back(reinterpret_cast<uintptr_t>(&trans));
141 }
142 check_properties(trans);
143 }
144 } else if(trans.is_read()) {
145 if(req_beat[tlm::TLM_READ_COMMAND]==tlm::UNINITIALIZED_PHASE) {
146 req_id[tlm::TLM_READ_COMMAND] = umax;
147 } else if(req_beat[tlm::TLM_READ_COMMAND]==tlm::BEGIN_REQ) {
148 if(req_id[tlm::TLM_READ_COMMAND] == umax) {
149 req_id[tlm::TLM_READ_COMMAND] = axi_id;
150 open_tx_by_id[tlm::TLM_READ_COMMAND][axi_id].push_back(reinterpret_cast<uintptr_t>(&trans));
151 } else if(req_id[tlm::TLM_READ_COMMAND] != axi_id){
152 SCCERR(name) << "Illegal phase: a read transaction uses a phase with id "<<req_beat[tlm::TLM_READ_COMMAND];
153 }
154 check_properties(trans);
155 } else {
156 SCCERR(name) << "Illegal phase: a read transaction uses a phase with id "<<req_beat[tlm::TLM_READ_COMMAND];
157 }
158 }
159}
160
161void ace_protocol::response_update(const payload_type &trans) {
162 auto axi_id = axi::get_axi_id(trans);
163 auto axi_burst_len = axi::get_burst_length(trans);
164 auto axi_burst_size = axi::get_burst_size(trans);
165 if(trans.is_write()){
166 if(resp_beat[tlm::TLM_WRITE_COMMAND]==tlm::UNINITIALIZED_PHASE) {
167 resp_id[tlm::TLM_WRITE_COMMAND] = umax;
168 } else if(resp_beat[tlm::TLM_WRITE_COMMAND]==tlm::BEGIN_RESP) {
169 if(resp_id[tlm::TLM_WRITE_COMMAND] == umax) {
170 resp_id[tlm::TLM_WRITE_COMMAND] = axi_id;
171 if(open_tx_by_id[tlm::TLM_WRITE_COMMAND][axi_id].front()!=reinterpret_cast<uintptr_t>(&trans)) {
172 SCCERR(name) << "Write response ordering violation: a response with AWID:0x"<<std::hex<<axi_id<<" starts before the previous response with the same id finished";
173 }
174 } else if(resp_id[tlm::TLM_WRITE_COMMAND] != axi_id){
175 SCCERR(name) << "Illegal phase: a read transaction uses a phase with id "<<resp_beat[tlm::TLM_WRITE_COMMAND];
176 }
177 open_tx_by_id[tlm::TLM_WRITE_COMMAND][axi_id].pop_front();
178 } else {
179 SCCERR(name) << "Illegal phase: a read transaction uses a phase with id "<<resp_beat[tlm::TLM_WRITE_COMMAND];
180 }
181 } else if(trans.is_read()) {
182 if(resp_beat[tlm::TLM_READ_COMMAND]==tlm::UNINITIALIZED_PHASE) {
183 resp_id[tlm::TLM_READ_COMMAND] = umax;
184 } else {
185 if(resp_id[tlm::TLM_READ_COMMAND] == umax) {
186 resp_id[tlm::TLM_READ_COMMAND] = axi_id;
187 if(open_tx_by_id[tlm::TLM_READ_COMMAND][axi_id].front()!=reinterpret_cast<uintptr_t>(&trans)) {
188 SCCERR(name) << "Read response ordering violation: a response with ARID:0x"<<std::hex<<axi_id<<" starts before the previous response with the same id finished";
189 }
190 rd_resp_beat_count[axi_id]++;
191 } else if(resp_id[tlm::TLM_READ_COMMAND] != axi_id){
192 SCCERR(name) << "Illegal phase: a read transaction uses a phase with id "<<resp_beat[tlm::TLM_READ_COMMAND];
193 }
194 if(resp_beat[tlm::TLM_READ_COMMAND]==tlm::BEGIN_RESP) {
195 if(rd_resp_beat_count[axi_id] != axi_burst_len){
196 SCCERR(name) << "Illegal AXI settings: number of transferred beats ("<<wr_req_beat_count<<") does not comply with AWLEN:0x"<<std::hex<<axi::get_burst_length(trans)-1;
197 }
198 auto mask = bw-1ULL;
199 auto offset = trans.get_address() & mask;
200 if(!offset){
201 if(trans.get_data_length() > (1 << axi_burst_size) * axi_burst_len) {
202 SCCERR(name) << "Illegal AXI settings: transaction data length (" << trans.get_data_length() << ") does not correspond to AxSIZE/AxLEN setting ("
203 << axi_burst_size << "/" << axi_burst_len-1 << ") for " << trans;
204 }
205 } else {
206 if((trans.get_data_length() + offset) >= (1 << axi_burst_size) * axi_burst_len) {
207 SCCERR(name) << "Illegal AXI settings: transaction data length (" << trans.get_data_length() << ") does not correspond to AxSIZE/AxLEN setting ("
208 << axi_burst_size << "/" << axi_burst_len-1 << ") for " << trans;
209 }
210 }
211 open_tx_by_id[tlm::TLM_READ_COMMAND][axi_id].pop_front();
212 rd_resp_beat_count[axi_id]=0;
213 }
214 }
215 }
216}
217
218constexpr unsigned comb(axi::bar_e bar, axi::domain_e domain, axi::snoop_e snoop){
219 return to_int(bar)<<10|to_int(domain)<<8|to_int(snoop);
220};
221
222void ace_protocol::check_properties(const payload_type &trans) {
223 if(auto* ace_ext = trans.get_extension<axi::ace_extension>()){
224 if(ace_ext->get_cache()&0xc0) {
225 if(!ace_ext->get_cache())
226 SCCERR(name)<<"Illegal ACEL settings: active allocate bit(s) requires modifiable bit set";
227 }
228 auto snoop = ace_ext->get_snoop();
229 auto domain = ace_ext->get_domain();
230 auto bar = ace_ext->get_barrier();
231 switch(comb(bar, domain, snoop)){
232 // Non-snooping
233 case comb(bar_e::RESPECT_BARRIER, domain_e::NON_SHAREABLE, snoop_e::READ_NO_SNOOP):
234 case comb(bar_e::RESPECT_BARRIER, domain_e::SYSTEM, snoop_e::READ_NO_SNOOP):
235 // Coherent
236 case comb(bar_e::RESPECT_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::READ_ONCE):
237 case comb(bar_e::RESPECT_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::READ_ONCE):
238 case comb(bar_e::RESPECT_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::READ_SHARED):
239 case comb(bar_e::RESPECT_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::READ_SHARED):
240 case comb(bar_e::RESPECT_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::READ_CLEAN):
241 case comb(bar_e::RESPECT_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::READ_CLEAN):
242 case comb(bar_e::RESPECT_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::READ_NOT_SHARED_DIRTY):
243 case comb(bar_e::RESPECT_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::READ_NOT_SHARED_DIRTY):
244 case comb(bar_e::RESPECT_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::READ_UNIQUE):
245 case comb(bar_e::RESPECT_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::READ_UNIQUE):
246 case comb(bar_e::RESPECT_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::CLEAN_UNIQUE):
247 case comb(bar_e::RESPECT_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::CLEAN_UNIQUE):
248 case comb(bar_e::RESPECT_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::MAKE_UNIQUE):
249 case comb(bar_e::RESPECT_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::MAKE_UNIQUE):
250 // Cache maintenance
251 case comb(bar_e::RESPECT_BARRIER, domain_e::NON_SHAREABLE, snoop_e::CLEAN_SHARED):
252 case comb(bar_e::RESPECT_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::CLEAN_SHARED):
253 case comb(bar_e::RESPECT_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::CLEAN_SHARED):
254 case comb(bar_e::RESPECT_BARRIER, domain_e::NON_SHAREABLE, snoop_e::CLEAN_INVALID):
255 case comb(bar_e::RESPECT_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::CLEAN_INVALID):
256 case comb(bar_e::RESPECT_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::CLEAN_INVALID):
257 case comb(bar_e::RESPECT_BARRIER, domain_e::NON_SHAREABLE, snoop_e::MAKE_INVALID):
258 case comb(bar_e::RESPECT_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::MAKE_INVALID):
259 case comb(bar_e::RESPECT_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::MAKE_INVALID):
260 // Barrier
261 case comb(bar_e::MEMORY_BARRIER, domain_e::NON_SHAREABLE, snoop_e::READ_NO_SNOOP):
262 case comb(bar_e::MEMORY_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::READ_ONCE):
263 case comb(bar_e::MEMORY_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::READ_ONCE):
264 case comb(bar_e::MEMORY_BARRIER, domain_e::SYSTEM, snoop_e::READ_NO_SNOOP):
265 // Non-snooping
266 case comb(bar_e::RESPECT_BARRIER, domain_e::NON_SHAREABLE, snoop_e::WRITE_NO_SNOOP):
267 case comb(bar_e::RESPECT_BARRIER, domain_e::SYSTEM, snoop_e::WRITE_NO_SNOOP):
268 // Coherent
269 case comb(bar_e::RESPECT_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::WRITE_UNIQUE):
270 case comb(bar_e::RESPECT_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::WRITE_UNIQUE):
271 case comb(bar_e::RESPECT_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::WRITE_LINE_UNIQUE):
272 case comb(bar_e::RESPECT_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::WRITE_LINE_UNIQUE):
273 // Memory update
274 case comb(bar_e::MEMORY_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::WRITE_CLEAN):
275 case comb(bar_e::MEMORY_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::WRITE_CLEAN):
276 case comb(bar_e::MEMORY_BARRIER, domain_e::SYSTEM, snoop_e::WRITE_CLEAN):
277 case comb(bar_e::MEMORY_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::WRITE_BACK):
278 case comb(bar_e::MEMORY_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::WRITE_BACK):
279 case comb(bar_e::MEMORY_BARRIER, domain_e::SYSTEM, snoop_e::WRITE_BACK):
280 case comb(bar_e::MEMORY_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::EVICT):
281 case comb(bar_e::MEMORY_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::EVICT):
282 case comb(bar_e::MEMORY_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::WRITE_EVICT):
283 case comb(bar_e::MEMORY_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::WRITE_EVICT):
284 case comb(bar_e::MEMORY_BARRIER, domain_e::SYSTEM, snoop_e::WRITE_EVICT):
285 // Barrier
286 case comb(bar_e::MEMORY_BARRIER, domain_e::NON_SHAREABLE, snoop_e::WRITE_NO_SNOOP):
287 case comb(bar_e::MEMORY_BARRIER, domain_e::INNER_SHAREABLE, snoop_e::WRITE_UNIQUE):
288 case comb(bar_e::MEMORY_BARRIER, domain_e::OUTER_SHAREABLE, snoop_e::WRITE_UNIQUE):
289 case comb(bar_e::MEMORY_BARRIER, domain_e::SYSTEM, snoop_e::WRITE_NO_SNOOP):
290 break;
291 default:
292 SCCERR(name)<<"Illegal ACE settings: According to D3.1.1 Read and write Shareable transaction types of ARM IHI 0022H the following setting is illegal:\n"
293 << "AxBAR:"<<to_char(bar)<<", AxDOMAIN:"<<to_char(domain)<<", AxSNOOP:"<<to_char(snoop);
294 }
295 switch(snoop) {
296 default:break;
297 case snoop_e::READ_CLEAN:
298 case snoop_e::READ_NOT_SHARED_DIRTY:
299 case snoop_e::READ_SHARED:
300 case snoop_e::READ_UNIQUE:
301 case snoop_e::CLEAN_UNIQUE:
302 case snoop_e::MAKE_UNIQUE:
303 case snoop_e::WRITE_LINE_UNIQUE:
304 case snoop_e::EVICT:
305 if(ace_ext->get_domain()==domain_e::NON_SHAREABLE) {
306 SCCERR(name)<<"Illegal ACE settings: According to D3.1.6 Transaction constraints of ARM IHI 0022H the following setting is illegal:\n"
307 << "AxDOMAIN:"<<to_char(ace_ext->get_domain());
308 }
309 /* no break */
310 case snoop_e::CLEAN_SHARED:
311 case snoop_e::CLEAN_INVALID:
312 case snoop_e::MAKE_INVALID:
313 case snoop_e::WRITE_EVICT:
314 if(ace_ext->get_domain()==domain_e::SYSTEM) {
315 SCCERR(name)<<"Illegal ACE settings: According to D3.1.6 Transaction constraints of ARM IHI 0022H the following setting is illegal:\n"
316 << "AxDOMAIN:"<<to_char(ace_ext->get_domain());
317 }
318 if(ace_ext->get_length() && (1u<<ace_ext->get_size()) != bw) {
319 SCCERR(name)<<"Illegal ACE settings: According to D3.1.6 Transaction constraints of ARM IHI 0022H the following setting is illegal:\n"
320 << "AxLEN:"<<static_cast<unsigned>(ace_ext->get_length())<<", AxSIZE:"<<static_cast<unsigned>(ace_ext->get_size())<<" with bus with:"<<bw;
321 }
322 auto width = bw;
323 switch(ace_ext->get_burst()) {
324 case burst_e::INCR:
325 width=(1+ace_ext->get_length())*(1u<<ace_ext->get_size());
326 /* no break */
327 case burst_e::WRAP:
328 if(trans.get_address()&(width-1)){
329 SCCERR(name)<<"Illegal ACE settings: According to D3.1.6 Transaction constraints of ARM IHI 0022H the following setting is illegal:\n"
330 << "AxBURST:"<<to_char(ace_ext->get_burst())<<", ADDR:0x"<<std::hex<<trans.get_address();
331 }
332 break;
333 case burst_e::FIXED:
334 SCCERR(name)<<"Illegal ACE settings: According to D3.1.6 Transaction constraints of ARM IHI 0022H the following setting is illegal:\n"
335 << "AxBURST:"<<to_char(ace_ext->get_burst());
336 }
337 if(ace_ext->get_barrier()!= bar_e::IGNORE_BARRIER) {
338 SCCERR(name)<<"Illegal ACE settings: According to D3.1.6 Transaction constraints of ARM IHI 0022H the following setting is illegal:\n"
339 << "AxBAR:"<<to_char(ace_ext->get_barrier());
340 }
341 if(!ace_ext->is_modifiable()) {
342 SCCERR(name)<<"Illegal ACE settings: According to D3.1.6 Transaction constraints of ARM IHI 0022H the following setting is illegal:\n"
343 << "AxCACHE:"<<static_cast<unsigned>(ace_ext->get_cache());
344 }
345 }
346 }
347}
348
349} /* namespace checker */
350} /* namespace axi */
axi
TLM2.0 components modeling AHB.
Definition axi_initiator.h:30
axi::to_char
const char * to_char(E t)
axi::get_burst_length
unsigned get_burst_length(const request &r)
Definition axi_tlm.h:1167
axi::domain_e
domain_e
Definition axi_tlm.h:85
axi::bar_e
bar_e
Definition axi_tlm.h:89
axi::bar_e::MEMORY_BARRIER
@ MEMORY_BARRIER
Normal access, respecting barriers.
Definition axi_tlm.h:91
axi::bar_e::IGNORE_BARRIER
@ IGNORE_BARRIER
Memory barrier.
Definition axi_tlm.h:92
axi::snoop_e
snoop_e
Definition axi_tlm.h:99
axi::to_int
constexpr ULT to_int(E t)
Definition axi_tlm.h:47
axi::get_burst_size
unsigned get_burst_size(const request &r)
Definition axi_tlm.h:1202